Motorola Corporation

Stuart E Greer

David Clegg

Suresh Venkatesan

Olubunmi O Adetutu

Douglas Michael Reber

Alexander Barr

Ramnath Venkatraman

Aubrey K Sparkman

Brian George Anthony

Terry E Burnette

Gregor Braeckelmann

Stephen R Crown

Rebecca G Cole

Robert A Munroe

Joel P Dietz

An interconnect overlies a semiconductor device substrate ( ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( ) overlies the conductive barrier layer and the passivation layer ( ) has an opening that exposes portions of the conductive barrier layer ( ). In an alternate embodiment a passivation layer ( ) overlies the interconnect, the passivation layer ( ) has an opening ( ) that exposes the interconnect and a conductive barrier layer ( ) overlies the interconnect within the opening ( ).

Method of forming semiconductor device including interconnect barrier layers

In accordance with one embodiment of the present invention, a semiconductor device underbump metallurgy ( ) is formed over a semiconductor bond pad ( ), wherein the underbump metallurgy ( ) comprises a chromium, copper, and nickel phased-region ( ), and wherein the presence of nickel in the phased-region ( ) inhibits conversion of tin from the solder bump and other tin sources from forming spallable Cu Sn copper-tin intermetallics.

Semiconductor device and method of formation

A mostly copper-containing interconnect ( ) overlies a semiconductor device substrate ( ), and a transitional metallurgy structure ( ) that includes an aluminum-containing film ( ) contacts a portion of the mostly copper-containing interconnect. In one embodiment, the transitional metallurgy is formed over a portion of a bond pad ( ). In an alternative embodiment, the transitional metallurgy includes an energy alterable fuse portion ( ) that electrically contacts two conductive regions ( and ), and in yet another embodiment, the transitional metallurgy is formed over a copper-containing edge seal portion ( ).

Method of forming copper interconnection utilizing aluminum capping film

Conductive bumps ( ) are formed to overlie a semiconductor die ( ). The conductive bumps ( ) typically have reduced levels of lead, flow at a temperature no greater than 260&deg; C., and have reduced problems associated with alpha particles. In one embodiment, the conductive bump ( ) includes a mostly tin ( ) with a relatively thin layer of lead ( ). The lead ( ) and a portion of the tin ( ) interact to form a relatively low melting solder close to the eutectic point for lead and tin. Most of the tin ( ) remains unreacted and can form a stand off between the semiconductor die ( ) and the packaging substrate ( ). Other metals and impurities can be used to improve the mechanical or electrical properties of the conductive bumps ( ).

Semiconductor device and a process for forming the semiconductor device

Multiplexed joining of solder bumps to various substrates for assembly of an integrated circuit package includes placing a semiconductor substrate (312) having solder bump structures (314) in contact with a ceramic substrate (320 having chip pads (322, 334), and placing this structure in contact with ball grid array spheres (352) in order to form a CBGA (360) in a single flow process. The method includes the steps of providing a semiconductor device having at least one first interconnect structure connected to a surface of the semiconductor device (501), and a substrate having a plurality of metallized pads (503); placing an at least one second interconnect structure in aligned contact with one or more of the plurality of metallized pads (505); placing the at least one first interconnect structure in aligned contact with one or more of the plurality of metallized pads (507); and simultaneously reflowing the at least one first interconnect structure and the at least one second interconnect structure such that the semiconductor device and at least one second interconnect structure are connected to the metallized pads of the substrate (509).

Method for multiplexed joining of solder bumps to various substrates

A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

Method for forming interconnect bumps on a semiconductor die

Flip-chip is fast becoming the mounting method of choice in the semiconductor industry for dice having a high number of contacts. Since many applications require known-good-die, these flip-chip semiconductor dice must be tested and burned-in. By testing and burning-in the semiconductor wafers prior to solder bumping, the probe tips (42, 44, 46 & 48) can contact the hard planar surface of the under-bump-metallurgy (40) on each bonding pad (14) for easier and more reliable contact and hence test results. The probe tips can be either of an array (42 & 44) or cantilevered needle (46 & 48) type. Blunt probe tips (42 & 48) are well-suited to making contact on the shoulder of each bonding pad of each semiconductor die, while sharp probe tips (44 & 46) are preferable for contacting the center of each bonding pad. Solder bumping is performed post-testing.

Method for testing and burning-in a semiconductor wafer

A semiconductor device (32) has an as-deposited solder bump (34) having the intrinsic potential for forming an extended eutectic region for simplified DCA applications. The as-deposited solder bump (34) has first tin layer (40) overlying the UBM of the bonding pad (14) on the device. The first tin layer reacts with a metal layer (36) in the UBM to form an intermetallic for adhering the solder bump to the bonding pad. A thick lead layer (42) overlies the first tin layer to provide the substantial component of the solder bump. A second tin layer (44) overlies the lead layer to provide localized eutectic formation at the top surface of the bump during reflow. A device having at least this solder bump structure can be directly attached to either ceramic or PC board substrates. Additional layers of tin and /or lead may be supplemented to the basic bump structure to optimize the eutectic formation rate.

Semiconductor device solder bump having intrinsic potential for forming

A nodular metal paste (42) is used to temporarily attach the bumps (34) on a semiconductor die (32) to a substrate (38). The spherical nodules (44) composing the metal paste are dispensed onto contact pads (40) on the substrate, and then heated until they partially melt. The partial liquid region permits bonding of the individual metal nodules to the contact pads and to adjacent nodules. Subsequently, a bumped die is placed over the nodules and heated to a minimum temperature required to partially remelt to form a local tack joint. Because the metallurgical contact area between the paste nodules and the bumps is minimized, electrical contact can be sustained with a small cross-sectional area of connected material to create an electrically sound but physically weak link between die and the substrate. Once connected to the substrate, the die may be tested and burned-in, and removed afterwards with little damage to the bumps.

Growing community of inventors

Austin, TX, United States of America

Stuart E Greer