Arm Limited

University of Michigan

Stuart David Biles

Richard Roy Grisenthwaite

Daniel Kershaw

Emre Özer

Nigel C Paver

David Hennah Mansell

Vladimir Vasekin

Krisztian Flautner

Matthew James Horsnell

Scott Mahlke

Nathan Clark

Bruce James Mathewson

Andrew Christopher Rose

Simon John Craske

Frederic Claude Marie Piry

Simon Andrew Ford

Graeme Peter Barnes

Antony John Harris

Christopher William Laycock

Yiannakis Sazeides

Norbert Bernard Eugéne Lataille

Richard York

Chander Sudanthi

David Theodore Blaauw

Michael John Williams

Dominic Hugo Symes

Thomas Christopher Grocutt

Trevor N Mudge

Dennis Sylvester

Antony John Penton

David Alan Fick

Paul Gilbert Meyer

Scott McLean Hanson

Alex James Waugh

Alastair David Reid

Stephen John Hill

Prakash Shyamlal Ramrakhyani

Emre Ozer

Paul Stanley Hughes

Philippe Jean-Pierre Raphalen

Christopher Bentley Dornan

Dam Sunwoo

Timothy Charles Mace

Donald Kenneth Felton

Wilco Dijkstra

Jocelyn Francois Orion Jaubert

Timothy Nicholas Hay

David Michael Gilday

Norbert Bernard Eugene Lataille

Elodie Charra

Gregory Kengho Chen

Geoffrey Wyman Blake

Viswanath Chakrala

Michael John Wieckowski

Andrei Kapustin

Kevin P Welton

Mrinmoy Ghosh

Yuri Levdik

Mélanie Emanuelle Lucie Vincent

Julie-Anne Francoise Marie Pruvost

Hedley James Frances

An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.

Apparatus and method for performing operations on capability metadata

Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.

Apparatus and method for managing capability metadata

An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register as it may be assumed that the lock value has already been checked.

Support apparatus and method for processing data and using hardware support for atomic memory transactions

A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

Cryptographic support instructions

A data processing system includes a plurality of transaction masters, each with an associated local cache memory and coupled to coherent interconnect circuitry. Monitoring circuitry within the coherent interconnect circuitry maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

Store-exclusive instruction conflict resolution

A hardware transactional memoryis provided within a multiprocessorsystem with coherency control and hardware transaction memory control circuitrythat serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.

Contention management for a hardware transactional memory

A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction.

Secure mechanism to switch between different domains of operation in a data processor

A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus

A data processing systemincludes a single instruction multiple data register fileand single instruction multiple processing circuitry. The single instruction multiple data processing circuitrysupports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.

A multi-threaded in-order superscalar processorincludes an issue stageincluding issue circuitryfor selecting instructions to be issued to execution unitsin dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitryand a selection between which of these instances of the policy circuitryis active is made by policy selecting circuitryin dependence upon detected dynamic behavior of the processor

Issue policy control within a multi-threaded in-order superscalar processor

A processoris provided with a plurality of hardware resources, such as performance monitorsand context pointers. Boundary indicating circuitrystores a boundary value which is programmable and which indicates a boundary position dividing the hardware resources into a first portion and a second portion. Resource control circuitrycontrols access to the hardware resources such that when program execution circuitryis executing a first program it is responsive to a query as to how many off said plurality of hardware resources are present to return a first value whereas when the program execution circuitry is executing a second program it responds to such a query by returning a value corresponding to those hardware resources within the second portion.

Hardware resource management within a data processing system

A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Fault handling in address translation transactions

A data processing system including a plurality of processorseach having a local cache memoryis provided. A cache coherency controllerserves to maintain cache coherency between the local cache memories. When one of the processorsis placed into a low power state its associated local cache memoryis maintained in a state in which the data it is holding is accessible to the cache coherency controlleruntil a predetermined condition has been met whereupon the local cache memoryconcerned is placed into a low power state. The predetermined condition can take a variety of different forms such as the rate of snoop hits falling below a threshold value, the ratio of snooping hits to snoop requests falling below a threshold value, a predetermined number of clock cycles passing since the associated processor for that local cache memory was powered down as well as other possibilities.

Local cache power control within a multiprocessor system

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Little Thurlow, United Kingdom

Stuart David Biles