International Business Machines Corporation

Stuart D Rapoport

Jean-Paul Mifsud

Luigi Ternullo, Jr

John P Connor

Garrett Stephen Koch

Robert Dean Adams

Herve L Beranger

Frederic Joly

Bertrand Gabillard

Thierry Cantiant

A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST structure with a redundancy mechanism. The circuit allows a two-pass fuse blow after completing the burn-in process that significantly increases the manufacturing yield and repairability of the SRAM macro.

Circuit for allowing a two-pass fuse blow to memory chips combining an

A processor-based Array Built-in Self Test (ABIST) circuit that generates self-test patterns for high speed SRAMs or DRAMs having a short access time. The circuit includes three main blocks: a conventional address generator for generating self-test addressing signals, a subset of which are used by a control logic main block. This control logic block forces proper signal sequencing of the processing main block during the ABIST mode. The processing main block includes, preferably, three generators for preparing signals for use during the next cycle. These signals are respectively stored in two latches to generate the corresponding expected output data one cycle later. The processor-based ABIST circuit allows for faster data generation, minimal semiconductor area consumption, extended programmability and full compatibility.

Integrated circuits with a processor-based array built-in self test

The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to 'ignore' such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory, and capture error information for that particular memory. Hence, a single BIST can be used to test a multiplicity of memories of different sizes and different types.

BIST tester for multiple memories

A fast high-density data compression circuit adapted to semiconductor integrated circuits of the memory type including an ABIST unit. This circuit, which compares the data-out signals output by the memory unit with the expected data generated by the ABIST unit to deliver a signal on a cycle by cycle basis, which is indicative of the fail/no fail status of the memory unit.

Fast data compression circuit for semiconductor memory chips including

An integrated circuit incorporating at least a SRAM that includes memory, a data-out shift register, an ABIST data compression circuit, a fail address register and an array clock generator (ACG), the ACG comprising a clock chopper that comprises a first AND gate having an inherent delay DEL1, a first input for receiving a D clock signal, a second input for receiving the D signal inverted by an invertor having an inherent delay DEL2, and an output that generates an ungated LSSSD C clock signal; and a second AND gate having an inherent delay DEL4, a first input connected to the output of an inverter having an inherent delay DEL3, the inverter is coupled to the invertor having the delay DEL2, a second input is controlled by the D clock signal and an output for generating LSSD clock signals B and S.

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New York, NY, United States of America

Stuart D Rapoport