Cadence Design Systems, Inc.

Stuart C Rae

Rahul Razdan

Andrew Robert Wilmot

Robert D Shur

Tuay-Ling Kathy Lang

David J Roberts

Edwin A Harcourt

Koushik Roy

Doug Dunlop

Bishnupriya Bhattacharya

Nadim Khalil

A method for simulation of mixed-language circuit designs is disclosed. In one embodiment, an object-oriented language module is natively instantiated within a hardware description language based design. In another embodiment, a hardware description language module is natively instantiated within an object-oriented language based design. A system for simulation of mixed-language circuit designs is also disclosed. In one embodiment, a simulator is configured to natively manipulate an object-oriented language module within a hardware description language based design. In another embodiment, a simulator is configured to natively manipulate a hardware description language module within an object-oriented language based design.

Method and system for simulation of mixed-language circuit designs

Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified.

Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques

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Jefferson, MA, United States of America

Stuart C Rae