International Telephone and Telegraph Corporation

Itt Defense Communications, a Division of Itt Corporation

Stuart Barry Cohen

James Monroe Clark

Arthur Howard Magnus

Robert H Haussmann

Arthur L Bandini

Robert Goeb

Ernest J Oliveira

A single fiber optical communication system (SFOCS) allows, in many operational scenarios, one-person deployment and recovery of optical links. Wavelength division multiplexing (WDM) is employed to provide full-duplex, bi-directional transmission. An optical subsystem achieves the wavelength multiplexing and demultiplexing while at the same time allowing for an unpolarized terminal design. Selection by the system of the WDM operating wavelengths between a pair of SFOCS terminals is performed without operator intervention.

Single fiber optical communication system

An asynchronous digital TDM multiplexer-demultiplexer combination at one communication terminal is capable of multiplexing N asynchronous input data signals having a random mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sum of the rates of the different rates and to demultiplex N asynchronous output data signals having the same random mixture of the different bit rates from a received synchronous data stream having the data format and the given bit rate, where N is an integer greater than 1. Each of the N channel printed circuit board plug-in receptacles, coupled to a different one of the N input data signals and a different one of N outputs each for a different one of the N output data signals, has plugged therein a selected one of no printed circuit boards, a digital data channel printed circuit board and an FSK channel printed circuit board to process a mixture of digital data signals, teletype signals and FSK signals in the N input data signals and the received data stream, with the mixture of signals being in any random order and mix and the digital channel printed circuit boards and the FSK channel printed circuit boards being plugged in the N receptacles in any random order and mix. The multiplexing and demultiplexing frame synchronization and automatic channel assignment is controlled by a programmable common controller so that the data bits of each of the N input data signals are distributed throughout the time slots of the transmitted and received data stream with equal spacing.

Asynchronous digital TDM multiplexer-demultiplexer combination

A common controller in the form of a programmed digital sequencer executes a series of instructions to control multiplexing-demultiplexing overhead channel format generation, frame synchronization stuff-destuff operation and automatic channel assignment in a digital TDM multiplexer-demultiplexer combination at one communication terminal to enable multiplexing N input data signals each having a predetermined bit rate into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the sum of the predetermined bit rates and to demultiplex N output data signals each having the predetermined bit rate from a received synchronous data stream having the data format and the given bit rate, where N is an integer greater than one. The disclosed common controller can be used with synchronous input and output data signals or for asynchronous input and output data signals wherein the asynchronous input and output data signals are distributed throughout the fixed data format in the time slots thereof evenly due to the automatic channel assignment. The programmed digital sequencer includes program memory means and support logic means coupled to the memory means to supply control signals in response to a plurality of digital codes present in the program memory means for multiplexing, demultiplexing, overhead channel format generation frame synchronization, stuff-destuff control and automatic channel assignment.

Programmable controller for a TDM digital multiplexer-demultiplexer

Each of first N flip-flop stages, where N is an integer greater than one, has steered thereto an appropriate one of N bits of the data to be transmitted by a transmit write counter and a first N stage decoder under control of a transmit write clock. A transmit read counter under control of a transmit read clock steers the stored bits to a transmit data bus by means of a first multiplexer and first logic circuitry under control of a transmit read counter and a transmit channel timing signal. Each of second N flip-flop stages has steered thereto an appropriate one of N bits of received data by a receive write counter and a second N stage decoder under control of a receive write clock. A receive read counter under control of a receive read clock steers the stored bits to a receive data bus by means of a second multiplexer and second logic circuitry under control of the receive read counter.

Transmit and receive digital data channel elastic store

An asynchronous digital time division multiplexer and demultiplexer combination at one communication terminal is disclosed that will multiplex first N asynchronous source data signals having a first mixture of different bit rates into a transmitted synchronous data stream having a predetermined fixed data format and a given bit rate greater than the total of the bit rates of the source data and to demultiplex second N asynchronous source data signals having a second mixture of different bit rates from a received synchronous data stream having the predetermined fixed data format and the given bit rate. The combination includes an automatic channel assignment circuit to assign channels of the two data streams to the asynchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates by assigning the data signals to channels of the associated one of the two data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the two data streams. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.

Asynchronous multiplexer and demultiplexer combination

A transmit phase locked loop receives data to be transmitted having a bit rate equal to a first given one of a predetermined number of different bit rates. A diphase demodulator responds to the transmit phase locked loop and the data to be transmitted to provide output data for transmission. A receive write timing signal and a receive read timing signal is coupled to a receive phase locked loop to compare the phase relation of the two timing signals. A diphase modulator responds to received data having a bit rate equal to a second given one of the predetermined number of different bit rates and a clock signal provided by the receive phase locked loop to provide output data for utilization. The first given one of different bit rates and the second given one of different bit rates may have equal or different bit rates.

Growing community of inventors

Nutley, NJ, United States of America

Stuart Barry Cohen