Silanna Asia Pte Ltd

Qualcomm Incorporated

Silanna Semiconductor U.s.a., Inc.

Io Semiconductor, Inc.

Brooktree Corporation

Qualcomm Switch Corp.

Semtech Corporation

The Silanna Group Pty Ltd

Silannapte Ltd

Stuart B Molin

Michael Andrew Stuber

Steven E Rosenbaum

Joseph Hubert Colles

Paul A Nygaard

Shanghui Larry Tu

Befruz Tasbas

Raymond Jiang

Chris Brindle

Mark Drucker

George P Imthurn

Perry Wyan Lou

Yashodhan Vijay Moghe

Peter Fowler

Clint L Kemerling

Anton Arriagada

James Douglas Ballard

Max Samuel Aubain

Laxminarayan Sharma

Sinan Goktepeli

Christopher Nelles Brindle

Jacek Korec

Boyi Yang

Clint Kemerling

Virgilio T Baterina

Michael A Stuber

A pulsed laser diode driver includes a source capacitor that receives a refresh current at a first terminal and develops a source voltage therefrom. A first terminal of an inductor is connected to the first terminal of the source capacitor. A second terminal of the inductor is connected to an anode of a laser diode and a bypass capacitor. One or more switches are configured to control a current flow through the inductor. A timing and control circuit is configured to receive the source voltage and to generate one or more gate driver signals to control the switches to produce a high-current pulse through the laser diode. The high-current pulse corresponds to a peak current of a resonant waveform developed at the anode of the laser diode. A timing of the one or more gate driver signals is based on a voltage level of the source voltage.

Auto flux timing for current resonant laser diode driver

A pulsed laser diode driver includes an inductor having a first terminal to receive a source voltage, and a second terminal, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor having a first terminal connected to the first terminal of the inductor and a second terminal connected to the second terminal of the inductor, a laser diode having a cathode that is connected to the first terminal of the inductor and an anode that is connected to the second terminal of the inductor, and a bypass switch connected between the second terminal of the inductor and ground. The bypass switch is configured to control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Single-FET pulsed laser diode driver

A pulsed laser diode driver includes multiple resonant laser diode driver cells, each cell including an inductor having a first inductor terminal to receive a source voltage, a source capacitor coupled between the first inductor terminal and ground, a bypass capacitor having a first terminal connected to the first inductor terminal and a second terminal connected to a second inductor terminal, a laser diode having a cathode that is connected to the first inductor terminal and an anode that is connected to the second inductor terminal, and a bypass switch connected between the second inductor terminal and ground. Each cell's bypass switch is configured to control a current flow through that cell's respective inductor to produce a high-current pulse through that cell's laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of that cell's laser diode.

A pulsed laser diode array driver includes an inductor having a first terminal configured to receive a source voltage, a source capacitor coupled between the first terminal of the inductor and ground, a bypass capacitor connected between a second terminal of the inductor and ground, a bypass switch connected between the second terminal of the inductor and ground, a laser diode array with one or more rows of laser diodes, and one or more laser diode switches, each being connected between a respective row node of the laser diode array and ground. The laser diode switches and the bypass switch are configured to control a current flow through the inductor to produce respective high-current pulses through each row of the laser diode array, each of the high-current pulses corresponding to a peak current of a resonant waveform developed at that row of the laser diode array.

Pulsed resonant laser diode array driver

A pulsed laser diode driver includes an inductor having a first terminal configured to receive a source voltage. A source capacitor has a first terminal connected to the first terminal of the inductor to provide the source voltage. A bypass switch has a drain node connected to a second terminal of the inductor and to a first terminal of a bypass capacitor. A laser diode switch has a drain node connected to the second terminal of the inductor. A laser diode has an anode connected to a source node of the laser diode switch and a cathode connected to a bias voltage node. The laser diode switch and the bypass switch control a current flow through the inductor to produce a high-current pulse through the laser diode, the high-current pulse corresponding to a peak current of a resonant waveform developed at the anode of the laser diode.

Pulsed laser diode driver

A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.

Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

A pulsed laser diode driver includes a refresh circuit configured to generate a refresh current using a received input voltage. A current amplitude of the refresh current is controlled by the refresh circuit based on a voltage level of a source voltage received by the refresh circuit. A source capacitor of the pulsed laser diode driver is configured to receive the refresh current and to develop the source voltage therefrom. An inductor of the pulsed laser diode driver has a first terminal that is directly electrically connected to the source capacitor. One or more switches of the pulsed laser diode driver are configured to control a current flow through the inductor to produce a high-current pulse through a laser diode that corresponds to a peak current of a resonant waveform developed at an anode of the laser diode.

Configurable high-frequency pulsed laser diode driver capacitor refresh circuit

An apparatus includes a first lateral diffusion field effect transistor (LDFET) having a first threshold voltage and that includes a first gate electrode, a first drain contact, a first source contact, and a first electrically conductive shield plate separated from the first gate electrode and the first source contact by a first interlayer dielectric. A second LDFET of the apparatus has a second threshold voltage and includes a second gate electrode, a second drain contact, and a second source contact. The second source contact is electrically connected to the first source contact of the first LDFET. A control circuit of the apparatus is electrically coupled to the first electrically conductive shield plate and is configured to apply to the first electrically conductive shield plate a first gate bias voltage of a first level to set the first threshold voltage of the first LDFET to a first desired threshold voltage.

Threshold voltage adjustment using adaptively biased shield plate

Configurable high-frequency pulsed laser diode driver

An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

Adaptive control of non-overlapping drive signals

A laser diode driver includes a clock terminal to receive a clock signal, configuration terminals to receive configuration data, drive terminals, and charging terminals. A first charging terminal is operable to charge a source capacitor of a resonant circuit that includes the source capacitor, an inductor, and a bypass capacitor. Each drive terminal is operable to be directly electrically connected to an anode or cathode of a laser diode or to ground. A mode, output selection, and grouping of drive signals that are delivered to the laser diodes are configured based on the configuration data. The laser diode driver is operable to control a current flow through the resonant circuit to produce high-current pulses through the laser diodes, the high-current pulses corresponding to a peak current of a resonant waveform developed at respective anodes of the laser diodes, a timing of the high-current pulses being synchronized using the clock signal.

Configurable pulsed laser diode driver

In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.

Noise-tolerant delay circuit

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Carlsbad, CA, United States of America

Stuart B Molin