Dell Products Inc.

Hewlett-packard Development Company, L.p.

Stuart Allen Berke

Bhyrav M Mutnury

Vadhiraj Sankaranarayanan

Minchuan Wang

John Erven Jenne

William Sauber

Sandor Tibor Farkas

Mark A Muccini

George Gilman Richards, Iii

Mukund Purshottam Khatri

Lei Wang

Hasnain Shabbir

Jordan Chin

Jeffrey Michael Lewis

Wade Andrew Butcher

Shane Michael Chiasson

Abey K Mathew

Douglas Winterberg

William Price Dawkins

Mark Edward Shaw

Shawn Joel Dube

Paul Theodore Artman

Gary Benedict Kotzur

John J Breen

Dinesh Kunnathur Ragupathi

Isaac Qin Wang

Dominick Adam Lovicott

Andrew Butcher

Ayedin Nikazm

Vivek Dharmadhikari

Ralph H Johnson

Kunrong Wang

Mehran Mirjafari

Mi Wang

Vadhiraj Sankaranarayanana

Corey Dean Hartman

Shiguo Luo

Eric Michael Tunks

Shawn Paul Hoss

Shyamkumar Thiyagarajan Iyer

Russ William Herrell

Guangyong Zhu

Balaji Bapu Gururaja Rao

Robert G Bassman

Sandeep Agarwal

Deepu Syam Sreedhar M

Sanjiv Sinha

William Draper

Dit Charoen

Padmanabh R Gharpure

William Kenneth Coxe, Iii

Amit Pratap Singh

Robert M Mondor

Ashish Razdan

William Coxe

Harry C Heinisch

John Evren Jenne

Jeffrey Guo

An information handling system includes a processor having a first data storage device in a first memory tier, a second data storage device in a second memory tier, and a tiering manager. The first tier exhibits first data storage attributes and the second tier exhibits second data storage attributes. The tiering manager receives first memory access information from the first data storage device and second memory access information from the second data storage device, makes a determination that a first performance level of the information handling system when first data is stored in the first data storage device can be improved to a second performance level of the information handling system by swapping the first data to the second data storage device based upon the first memory access information and the second memory access information, and swaps the first data to the second data storage device in response to the determination.

Distributed region tracking for tiered memory systems

A tiered memory system includes a tiered memory management system that is coupled to a first memory subsystem associated with a first memory subsystem tier, and a second memory subsystem associated with a second memory subsystem tier that is different than the first memory subsystem tier. The tiered memory management system monitors a health of the first memory subsystem associated with the first memory subsystem tier and the second memory subsystem associated with the second memory subsystem tier. When the tiered memory management system identifies a health issue with the first memory subsystem associated with the first memory subsystem tier, it moves data stored in the first memory subsystem associated with the first memory subsystem tier to the second memory subsystem associated with the second memory subsystem tier.

Tiered memory management system

An information handling system includes a first memory device that provides a first system physical address (SPA) space for the information handling system having a first capacity. Data is stored on the first memory device with a first interleave configuration. A second memory device provides a second SPA space for the information handling system that has a second capacity that is greater than or equal to the first capacity. Without rebooting the information handling system and without halting a process, the system de-interleaves the data stored on the first memory device, stores the data on the second memory device, and re-interleaves the data.

Runtime de-interleave and re-interleave of system memory

An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

Method for CXL fallback in a CXL system

An information handling system includes a compute express link (CXL) device coupled to a processor by a PCIe/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a CXL link signaling rate, trains the PCIe/CXL link as a PCIe link in response to determining that the PCIe/CXL link failed to train to the CXL link signaling rate, and operates the CXL device as a PCIe device only in response to training the PCIe/CXL link as a PCIe link.

Method for PCIe fallback in a CXL system

An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.

Providing cache line metadata over multiple cache lines

An information handling system includes first and second memory modules, and a central processing unit. The first memory module includes one or more memory ranks of memory devices, and a first plurality of thermal sensors. The second memory module includes one or more memory ranks of memory devices, and a second plurality of thermal sensors. The central processing unit receives first thermal telemetry data for the first memory module from the first thermal sensors, and second thermal telemetry data for the second memory module from the second thermal sensors. In response to the reception of the first thermal telemetry data, the central processing unit determines a first localized temperature of a first memory rank. In response to the first localized temperature exceeding a threshold temperature, the central processing unit re-maps access of data from the first memory rank to a second memory rank.

System and method for utilizing enhanced thermal telemetry for differential storage of data on a memory module

An information handling system includes a memory module having a first thermal sensor for a first memory channel, and a second thermal sensor for a second memory channel. A processor receives a first temperature from the first thermal sensor and a second temperature from the second thermal sensor, and performs a first high bandwidth access of the first memory channel. In response to a predetermined amount of time ending, the processor: receives a third temperature from the first thermal sensor and a fourth temperature from the second thermal sensor; determines a first temperature delta based on a difference between the third and first temperatures; and determines a second temperature delta based on a difference between the fourth and second temperatures. Based on the first and second temperature deltas, the processor determines whether the first or second memory channel is an upstream memory channel.

System and method for determining physical orientation of a memory module using on-board thermal sensors

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

System and method for providing per channel frequency optimization in a double data rate memory system

An information handling system includes a processor that runs a maximum memory stress test of a memory module with a refresh rate of memory devices set to a first refresh rate. Then, the processor may receive a power consumption of the memory module. Also, the processor may receive the temperature of the memory devices, and may set the refresh rate to a second refresh rate. The processor may continuously receive both the power consumption of the memory module and the temperature of the memory devices. Based on the continuously received temperature, the processor may determine whether the temperature of the memory devices exceeds a second threshold temperature. If so, the processor may store a first setting as a refresh setting for the memory module. Otherwise, the processor may store a second setting as the refresh setting for the memory module.

System and method for optimizing system power and performance with high power memory modules

An memory subsystem of an information handling system includes a memory module and a controller. The memory module includes a Registering Clock Driver (RCD) configured to receive a clock signal. The RCD includes a delay setting and a clock delay circuit to provide a selectable delayed clock signal based upon the delay setting. The memory module further includes a power management integrated circuit (PMIC) with a plurality of switching regulators. The PMIC receives the delayed clock signal and clocks the switching regulators based upon the delayed clock signal. The controller sets the first delay setting.

System and method for power plane noise reduction in a memory subsystem of an information handling system

In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.

System and method of rerouting an inter-processor communication link based on a link utilization value

An information handling system includes a power assist unit (PAU) and a baseboard management controller (BMC). The PAU is coupled to a power rail and includes a power storage element, a converter coupled to the power storage element and the power rail, and a controller. The controller receives a current level indication indicating a current provided to a load of the information handling system, directs the converter to provide power from the power storage element to the power rail when the current level indication is greater than a threshold level, directs the converter charge the power storage element from the power rail when the current level indication is greater than the threshold level, and provides a charge level indication that indicates an amount of charge on the power storage unit. The BMC receives the charge level indication, and sets a peak power limit for the information handling system based on the charge level indication.

Method and apparatus to provide platform power peak limiting based on charge of power assist unit

A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

System and method to dynamically increase memory channel robustness at high transfer rates

An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (V) setting for bidirectional communications with the CPU.

System and method for variable input output voltage on different channels for increasing power efficiency

Growing community of inventors

Austin, TX, United States of America

Stuart Allen Berke