Adaptec, Inc.

Stillman F Gates

Christopher R Burns

Uday N Devanagundy

Salil Suri

Paresh M Borkar

Fadi A Mahmoud

Charles S Fannin

Ross John Stenfort

Paul J Von Stamwitz

Taikhim Henry Tan

Byron Arlen Young

Craig A Stuber

Jamileh Davoudi

Douglas K Makishima

Daniel A Dawson

Tracy Kahl

Broadly speaking, a method and apparatus is provided for identifying and responding to a deadlock condition in a SAS/SATA communication process. More specifically, an initiator device involved in the SAS/SATA communication process is defined to recognize a received error signal as an indication of a potential communication deadlock condition. The initiator device is further defined to promptly respond to the received error signal with a course of action for recovering from the communication deadlock condition.

Method and apparatus for handling SAS/SATA communication deadlock

A method for configuring channels of a dual channel SCSI chip is provided which includes setting at least one bit in a first configuration space within a first channel control in the dual channel SCSI chip where the first configuration space returns a device identification information when accessed by an operating system. The method also includes setting at least one bit in a second configuration space within a second channel control in the dual channel SCSI chip where the second configuration space returns data indicating that the second configuration space does not contain any device identification information when accessed by the operating system. The first channel control is detected and managed by the operating system, and the second channel control is not detected by the operating system and is managed by a device processor.

Methods for configuring separate accessibility of each channel of a dual channel SCSI chip

A method for utilizing a multi-channel SCSI chip capable of controlling different types of devices is disclosed. A first channel control is set and a second channel control is set in the SCSI chip. A first peripheral device type is managed using the first channel control and a second peripheral device type is managed using the second channel control.

Dual-channel SCSI chips and methods for configuring separate interoperability of each channel of the SCSI chip

A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit that interfaces to various resources that are included in a support circuit. The serial port forms a packet from each byte of information to be transferred from a module to the slave device by adding a start bit before the byte, followed by a parity bit at the end of the byte and followed by a stop bit. After transmitting the packet, the serial port waits for an acknowledge packet from the slave serial port input-output integrated circuit, for example for two clock cycles after transmission of the packet. For synchronous operation, a common oscillator drives the clock signal on the slave serial port input-output integrated circuit and host adapter integrated circuit. The serial port pin in the host adapter integrated circuit is connected to a shifter circuit in the serial port that serially clocks data from the serial port pin and passes the data parallelly to a bus in the host adapter integrated circuit and vice versa.

Serial bus for connecting two integrated circuits with storage for input/output signals

A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Source-destination re-timed cooperative communication bus

A processor includes a stack that operates as a circular stack and appears to the address space in the memory of the processor as a single point address location. The stack supports read and write data access functions in addition to CALL (push) and RETURN (pop) programming operations. The processor may be programmed to save the stack in a typical manner with one instruction atomically transferring each element in the stack directly from the stack to a save storage. To restore the stack, the processor may be programmed to individually restore each element. The processor supports a special MOV instruction that transfers a plurality of bytes in a single operation. The special MOV instruction has one argument that identifies the beginning transfer source address, another argument defines the byte count indicating the number of bytes to be transferred, and a beginning transfer destination address. The processor may be programmed to perform a stack save operation with only a single instruction that moves the contents of the stack to the save storage. To further reduce context switching time and reduce the stack save and restore operation to a minimum number of instructions while maintaining the proper entry relationship for both stack read and write operations, the processor includes a &ldquo;stack read forward&rdquo; option to the special MOV instruction. The option to the special MOV instruction operates to read data in a forward direction even when no valid data is stored in the locations. The read operation begins at the start address specified by an argument to the MOV instruction, reads forward, and wraps around in a binary fashion back to the start address.

Fast stack save and restore system and method

Apparatus and method for communication between integrated circuit connected to each other by a single line

Serial port for a hose adapter integrated circuit using a single terminal

An integrated circuit includes a monitor port, several circuit modules, and a selection circuit that selects which of the circuit modules drives internal signal through the monitor port. A debugging process can observe the internal signals at the monitor port to identify problems in the integrated circuit. In one embodiment, the selection circuit includes a trace bus that runs serially from the monitor port to each circuit module. Each module has tri-state buffers that connect the module to the trace bus. Alternatively, the selection circuit includes a multiplexer with input ports coupled to the modules. A trace select register controls which module drives the monitor port, and control registers or the current operation of each module select which set of internal signals the module applies to the tri-state buffers. Any of large number of internal signals can be selected and observed by programming the trace select register and the configuration registers for the modules. In one embodiment, the integrated circuit is a host adapter that includes modules operating in different clock domains.

Monitor port with selectable trace support

A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To permit parallel flow-through operation, each of the two buffers is organized into a number of fixed-sized pages that are accessible via the peripheral bus only one page at a time. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two pages in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses one page to hold data that is currently being received, while using another page containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g. peripheral device address, or system memory address or a sequence identifier of a Fiber Channel frame) of the data. Specifically, each data path uses one page to hold data that is currently being received from one context, while using another page containing data of another context that was previously received for simultaneous transmission from the host adapter.

Host adapter having paged payload buffers for simultaneously transferring data between a computer bus and a peripheral bus

A memory architecture for a circuit such as a host adapter provides sections of memory used for different types of information and programmable sizes for the sections. Thus, the circuit can adapt memory configurations for different applications. Each section is divided into pages, and for each section, the circuit has a range of internal addresses that map to a current page in the section. Additionally, the circuit has several operating modes and several register sets. Each mode has a set of functions that the circuit performs and a register set that the circuit can access while operating in the mode. Currently accessible pages in the memory are selected according to the operating mode. In particular, the register sets include registers for pointers that identify pages currently accessible. When the circuit switches modes, the accessible register set changes, and changing the register set changes the pointers and which pages are accessible. Generally, the accessible register set and memory pages are selected according to the function of the mode. Accordingly, the internal address space for accessing registers and memory can be minimized, since only the registers and pages needed for the functions of a mode are accessible while the circuit operates in the mode.

Host adapter having a plurality of register sets and corresponding operating nodes

A host adapter has receive and transmit data paths, each of which includes a buffer (formed of storage elements) for temporarily holding the data being transferred by the host adapter. The host adapter uses each of the two buffers for storing only the data being transferred in the respective direction, each independent of the other, for full-duplex data transfer therethrough. To maximize bandwidth and minimize latency, during operation in any given direction of data transfer (e.g. from the computer bus to the peripheral bus or vice versa) the host adapter uses at least two memory portions in a data path simultaneously: one for receipt and another for transmission. Specifically, each data path uses a memory portion to hold data that is currently being received, while using another memory portion containing data that was previously received for simultaneous transmission from the host adapter. Each of the data paths transfers data in a continuous manner irrespective of the context (e.g. peripheral device address, or system memory address or a sequence identifier of a Fibre Channel frame) of the data.

Host adapter capable of simultaneously transmitting and receiving data of multiple contexts between a computer bus and peripheral bus

A host adapter integrated circuit has a dedicated circuit which detects an attempted access of a digital resource (for example, SCSI bus interface circuitry) from a system bus (for example, a PCI bus) and automatically generates a pause request signal to stop instruction execution of a sequencer of the host adapter integrated circuit. The sequencer stops executing instructions, the sequencer is decoupled from the digital resource, and the digital resource is coupled to the system bus. With the digital resource coupled to the system bus, the system bus access of the digital resource is completed. In some embodiments, a pause acknowledge signal is generated by bus transfer logic of the sequencer to indicate that the digital resource can be accessed from the system bus. This pause acknowledge signal is used to generate a ready signal onto the system bus. The digital resource is therefore accessed from the system bus in one system bus cycle, an attempted access by a device on the system bus is not interrupted by another device on the system bus, and the accessing device need perform no special polling.

Host adapter integrated circuit having autoaccess pause

A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on a expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

An integrated circuit such as a host adapter for connection to a system bus of a host computer includes a memory interface for a local memory including a serial memory such as an SEEPROM. The memory interface is capable of unsupervised multi-bit transfers between the serial memory and a data register in the memory interface. The host computer to access the serial memory starts the memory interface on a multi-bit access (i.e., read, write, or erase), checks a busy bit in the memory interface to determine when the access is complete, and accesses the data register. Thus, the host computer is decoupled from bit-by-bit management of transfers, and the integrated circuit or a bus device incorporating the integrated circuit requires less software overhead for use of serial memory. The memory interface further includes protection circuitry that prevents writing or erasing of a portion of the memory that a flag designates as protected. The flag is in a register that does not permit changes unless the host adapter is in a state such as corresponding to a target abort exists. Accordingly, the host can write or erase protected memory by causing a target abort, changing the flag to unprotect the memory, and then changing the memory. Since the state is unlikely to exist when a software might unintentionally access the flag, unintended changes to the protected memory are unlikely.

Growing community of inventors

Los Gatos, CA, United States of America

Stillman F Gates