Stmicroelectronics S.a.

Stmicroelectronics International N.v.

Stmicroelectronics S.r.l.

Stmicroelectronics Pvt. Ltd.

Stmicroelectronics (alps) Sas

Stmicroelectronics (canada), Inc.

Stéphane Le Tual

Pratap Narayan Singh

Loïc Joet

Jean-Pierre Blanc

Denis Pache

Eoin Ohannaidh

Mounir Boulemnakher

David Duperray

Jean-François Roux

Jean-Louis Coutaz

Oleksiy Zabroda

Nicola Vannucci

A sampling circuit includes a metal oxide semiconductor (MOS) transistor that includes a third metallization receiving a reference voltage between a first metallization coupled to a source region of the transistor and a second metallization coupled to a drain region of the transistor.

Sampling circuit

A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

Variable delay element

The invention concerns a circuit comprising: a first circuit block () adapted to receive a first clock signal (CLK) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block () adapted to receive a second clock signal (CLK) and to provide a second output data signal at a time determined by said second clock signal; a clock bus () coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit () coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Data synchronization circuit

The invention concerns a circuit comprising: a first transistor () having a first main current node coupled to a first voltage signal (CN), a control node coupled to a second voltage signal (CP) and a second main current node coupled to an output node () of the circuit; a second transistor () having a first main current node coupled to a third voltage signal (CN), a control node coupled to a fourth voltage signal (CP) and a second main current node coupled to said output node of the circuit; and circuitry () adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).

Circuit and method for signal conversion

The invention concerns a circuit comprising: a first transistor () having first and second main current nodes, and a gate node adapted to receive a first timing signal (CLK) for causing the first transistor to transition between conducting and non-conducting states; a biasing circuit () coupled to a further node of said first transistor; and a control circuit () adapted to control said biasing circuit to apply a first control voltage (V) to said further node to adjust the timing of at least one of said transitions.

Circuit and method for skew correction

A method of successive approximation analog to digital conversion including: during a sample phase, coupling an input signal to a plurality of pairs of capacitors; and during a conversion phase, coupling a first capacitor of each pair to a first supply voltage, and a second capacitor of each pair to a second supply voltage.

Compact SAR ADC

A differential successive approximation analog to digital converter including: a comparator; a first plurality of capacitors coupled between a corresponding plurality of first switches and a first input of the comparator, at least one of the first capacitors being arranged to receive a first component of a differential input signal; and a second plurality of capacitors coupled between a corresponding plurality of second switches and a second input of the comparator, at least one of the second capacitors being arranged to receive a second component of the differential input signal, wherein each of the first and second plurality of switches are each adapted to independently couple the corresponding capacitor to a selected one of: a first supply voltage level; a second supply voltage level; and a third supply voltage level; and control circuitry adapted to sample the differential input voltage during a sample phase, and to control the first and second switches to couple each capacitor of the first and second plurality of capacitors to the third supply voltage level at the start of a voltage conversion phase.

Differential successive approximation analog to digital converter

A common-source circuit including two branches in parallel between a terminal of application of a voltage and a current source, each branch comprising: a series association of a resistor and a transistor, having their junction point defining an output terminal of the branch; a first switch connecting an input terminal of the branch to a control terminal of the transistor; and a controllable stage for amplifying data representing the level present on the output terminal of the opposite branch.

Bistable CML circuit

An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Analog FIR filter

The method and device include the filtering and the analog/digital conversion of an intermediate signal. The intermediate signal is processed by a filtering and analog/digital conversion circuit that is configurable using switched passive capacitor technology. The various configurations successively adopted by the circuit provide filtering and analog/digital conversion to be successively carried out.

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Saint Egreve, France

Stéphane Le Tual