International Business Machines Corporation

Steven William Tomashot

Nathan R Hiltebeitel

John Atkinson Fifield

Robert Tamlyn

Claude Louis Bertin

William R Tonti

Russell J Houghton

Toshiaki Kirihata

Timothy Dooling Sullivan

William Paul Hovis

Erik L Hedberg

Christopher P Miller

Dale E Pontius

David G Chapman

Timothy E Fiscus

Erik A Nelson

Alan D Norris

Satish Gupta

Todd Williams

Randall L Henderson

Jim L Rogers

David P Monty

Paul William Coteus

Warren Edward Maule

Oscar Frederick Jones, Jr

Kenneth J Mobley

David W Bondurant

Timothy J Ebbers

Thomas W Wyckoff

William E Corbin, Jr

Michael Curtis

William R Corbin

Robert Henry Kruggel

A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices

To overcome these problems, the present invention generates two window strobes and uses the two window strobes to determine if skew between two signals meets predetermined criteria. One of the window strobes is used to test one of the signals, and the other window strobe is generated relative to the first window strobe. The second window strobe tests the other signal (or signals, if they are data signals). From the tests of the two window strobes, it can be determined if the skew between the first and second signals meets predetermined criteria. In particular, the two window strobes are placed relative to each other and to the signals being tested in such a way that when both window strobes indicate passing conditions, skew between the two signals is guaranteed.

Method for testing and guaranteeing that skew between two signals meets predetermined criteria

An improved and much simplified method to access data banks in a memory system which provides the option of opening more than one bank in a single command. This is especially useful to achieve bursts of data across bank boundaries in a memory system of synchronous dynamic random access memory cards having fast memory bus speeds. The method decodes signals to generate a single command which may open one or more memory bank at a time. Logic can increment the banks, decrement a bank counter, and, if necessary, increment/decrement a row and/or uniquely address a column so that continual data bursts can be achieved seamlessly across bank boundaries in synchronous dynamic random access memory systems. The data banks may be opened all at once, or can be opened sequentially in a staggered manner according to a synchronous or asynchronous, with respect to the memory clock, time delay During that time delay a nop command or a chip deselect command may execute.

Multiple memory bank command for synchronous DRAMs

A clocked memory device includes a programming mechanism that allows the write recovery time during a command with auto precharge enabled to be dynamically set to some function of the input clock. In the preferred embodiments, the programming mechanism includes a control register with programmable bits that allows specifying the write recovery time according to the bit values written to the control register. For example, write recovery time could be specified as a whole or fractional number of clock cycles. By specifying the write recovery time as a function of the clock that may be dynamically set, the clocked memory device may be used at its highest performance capabilities over a wide range of operating frequencies.

Clocked memory device that includes a programming mechanism for setting write recovery time as a function of the input clock

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.

Cached synchronous DRAM architecture having a mode register programmable cache policy

A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.

Impedance control using fuses

A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

Capacitive precharging and discharging network for converting N bit input into M bit output

A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices. Therein, the relation between the system memory data bus and the memory data ports for the memory devices are recognized by a memory controller. A microprocessor in the electric system is used for testing the memories and for analyzing the redundancy address. The present invention further includes a post device identification protocol to effectively debug field problems.

Memory and system configuration for programming a redundancy address in an electric system

An invention is disclosed which implements bit line redundancy in a memory module, such as a dynamic random access memory (DRAM), in accordance with a block write operation. The block write operation is commonly used in dual port RAMs, sometimes referred to as video random access memories (VRAM). Specifically, a block write operation allows a plurality of bits of data to be written to a plurality of adjacent bit lines defined by a column address. The precise combination of adjacent bit lines selected by the column address is designated by an address mask. The invention provides a memory module with a redundant bit decoder that incorporates an address masking function into the redundant bit decoder during block write operations and also bypasses a masking function during normal read and write operations. This redundant bit decoder allows a single redundant bit line to replace any single defective bit line of the selected group of block write bit lines. It eliminates the need for replacing all the selected bit lines and, thereby, saves silicon area and maximizes the utilization of available redundant bit elements.

Redundancy architecture and method for block write access cycles

A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data. A randomly addressable row register stores a row of data latched by the sense amplifiers. A select logic gating means, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed. Data to be input into the cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array. Data to be output from the cached SDRAM during a Read command is read out only from the row register, the row of data contained in the row register first having been read from the memory bank array to the sense amplifiers and then selectively gated to the row register in accordance with the particular synchronous memory operations.

Cached synchronous DRAM architecture allowing concurrent DRAM operations

An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.

Address transition detector (ATD) for power conservation

A fuse download system for programming decoders for redundancy. Auxiliary fuse banks have sets of fuses that store logic states that (a) select a redundant decoder and (b) indicate the address of a faulty row/column of memory cells. When the chip is first powered up, each set of fuses is accessed and downloaded to program selected redundant decoders. Because the fuse sets can be dynamically assigned to redundant decoders on an any-for-any basis, the fault tolerance of the redundancy system is enhanced.

Flexible redundancy architecture and fuse download scheme

An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial access memory register, data from each of the two frame buffers is available. A double buffer select signal controls the selection of which half of the serial access memory register will put data on the output bus for each serial clock signal. The serial clock increments the address pointers in both halves of the serial access memory port simultaneously.

Video RAM double buffer select control

A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

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Williston, VT, United States of America

Steven William Tomashot