Data General Corporation

Steven Wallach

Kenneth D Holberger

Charles J Holland

Carl J Alsing

Michael L Ziegler

James Marriot Guyer

Michael B Druke

David L Keating

Richard W Coyle

Carl Henry

Edward J Rasala

Steven M Staudaher

Thomas West

Steven M Staudaner

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Data processing system having a unique address translation unit

A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The instruction responsive apparatus thereof responds to unique microinstructions which, for example, provide for the selection of one of a plurality of interrupt routines each corresponding to an interrupt request from a different external device, provide for the sequential loading of a plurality of segment identification registers each pointing to selected memory management tables associated with a segment storage region of main memory, provide for a program counter relative jump operation, provide for zero-extending or sign-extending 16-bit words to 32-bit words having the same value, and provide for the multiplication of the lower 16 bits of two 32-bit accumulators and the sign-extension of the 16-bit result to form a 32-bit word.

Data processing system having instruction responsive apparatus for both

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses. The system uses hierarchical memory storage using in a particular embodiment eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The segment locations are designated by successive segment numbers having a descending order of protection with reference to data accesses thereto. A current address for data access includes a segment identification and a comparison is made with the segment identification of a preceding address to determine whether access can be made by the current address.

Hierarchial memory ring protection system using comparisons of requested

Data processing system

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Framingham, MA, United States of America

Steven Wallach