Tandem Computers Incorporated

Hewlett-packard Development Company, L.p.

Steven W Wierenga

David A Greig

James A Katzman

John A Despotakis

William H Davidow

Richard M Bixler

Dennis L McEvoy

Peter J Graziano

Joel F Bartlett

James G Treybig

David R Mackie

Steven J Hayashi

Michael D Green

Thomas W Collins

W Dale Hopkins

Susan K Langford

Jeff Kalibjian

Dale W Hopkins

Larry M Hines

Vladimir Libershteyn

A Richard Zacher

Ralph Bestock

Steven D Fisher

John W Clark

Ruth A Wang

Jon Sjostedt

Richard A Humphrey

David J Lilja

In one embodiment, a method of implementing trusted compliance operations inside secure computing boundaries comprises receiving, in a secure computing environment, a data envelope from an application operating outside the secure computing environment, the data envelope comprising data and a compliance operation command, verifying, in the secure computing environment, a signature associated with the data envelope, authenticating, in the secure computing environment, the data envelope, notarizing, in the secure computing environment, the application of the command to the data in the envelope, executing the compliance operation in the secure environment; and confirming a result of the compliance operation to a client via trusted communication tunnel.

Trusted compliance operations inside secure computing boundaries

Systems, methods, and apparatus are provided for policy protected cryptographic Application Programming Interfaces (APIs) that are deployed in secure memory. One embodiment is a method of software execution. The method includes executing an application in a first secure memory partition; formatting a request to comply with a pre-defined secure communication protocol; transmitting the request from the application to a cryptographic application programming interface (API) of the application, the API being in a second secure memory partition that is separate and secure from the first secure memory partition; and verifying, in the second secure memory partition, that the request complies with a security policy before executing the request.

Policy based cryptographic application programming interface in secure memory

A method is disclosed for performing cryptographic tasks, that include key setup tasks and work data processing tasks. This method comprises the steps of processing the key data in a first cryptographic engine and processing the work data in a second cryptographic engine. The processing of the key data comprises the steps of receiving key data, processing the key data, and generating processed key data. The processing of the work data comprises the steps of receiving the processed key data, receiving work data, processing the work data, and outputting the processed work data. In this method of the invention, the first cryptographic engine performs its tasks independently of the second cryptographic engine. A method for allocating cryptographic engines in a cryptographic system is also disclosed comprising monitoring a queue of cryptographic tasks, monitoring activity levels of a first allocation of a plurality of cryptographic engines, and dynamically adjusting the first allocation.

Cryptographic key setup in queued cryptographic systems

A process is provided for searching in parallel for a plurality of prime number values simultaneously includes the steps of: randomly generating a plurality of k random odd numbers (wherein k is preferably more than 2, but could also be one or more) expressed as n, n, . . . n, each number providing a prime number candidate; determining a plurality of y additional odd numbers based on each one of the randomly generated odd numbers n, n, . . . nto provide additional prime number candidates thereby yielding a total number of prime number candidates; sieving the total number of prime number candidates by performing a small divisor test on each of the candidates in order to eliminate candidates revealed to be composite numbers by the small divisor test thereby yielding a sieved number s of candidates; and performing a first probabilistic primality test on each of the sieved number s of candidates, each of the plurality of s first primality tests including an associated exponentiation operation executed by an associated one of a plurality of s of the exponentiation units, the exponentiation operations being performed by the plurality of s exponentiation units substantially simultaneously in order to eliminate candidates revealed to be composite numbers by the primality test thereby yielding a remaining number r of candidates.

Multiple prime number generation using a parallel prime number search algorithm

A method is provided for generating a group digital signature wherein each of a group of individuals may sign a message M to create a group digital signature S, wherein M corresponds to a number representative of a message, 0&#x2266;M&#x2266;n&#x2212;1, n is a composite number formed from the product of a number k of distinct random prime factors p&#xb7;p&#xb7; . . . &#xb7;p, k is an integer greater than 2, and S&#x2261;M(mod n). The method may include: performing a first partial digital signature subtask on a message M using a first individual private key to produce a first partial digital signature S; performing at least a second partial digital signature subtask on the message M using a second individual private key to produce a second partial digital signature S; and combining the partial digital signature results to produce a group digital signature S.

Group signature generation system using multiple primes

A method and apparatus provides cryptographic parameters for use in cryptographic applications in response to requests therefor. The method includes the steps of: pre-computing one or more different types of sets of cryptographic parameters, each the type of set being adapted for use by an associated type of cryptographic application; securely storing the pre-computed sets of cryptographic parameters in a memory storage unit; receiving a request for a set of cryptographic parameters having specified characteristics for use in a particular cryptographic application; determining one of the sets of cryptographic parameters stored in the memory storage unit that has specified characteristics; accessing the determined set of cryptographic parameters from the memory storage unit; and providing the determined set of cryptographic parameters with minimal latency.

Multiple cryptographic key precompute and store

A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.

Multiprocessor bus protocol

In a multiprocessor system interconnected by a bus structure that provides communication and information transfers between the processor modules of the system, each processor broadcasts a central message to all the other processors of the system on a periodic basis. A processor module not receiving the control message from a sending processor module will assume the sending processor module has failed, and operate to take over the task of the failed processor module.

Fault-tolerant multiprocessor system

In a multiprocessor system comprising a plurality of individual processor modules interconnected by a bus structure, including a bus controller, for providing communication between the processor modules, a method and apparatus for interprocessor communication includes one of the processor modules sending a request signal to the bus controller to request a transmission; the bus controller polling the processor modules to identify the requesting processor module; the requestor processor module responding to the poll with the identification of the receiver processor module; the bus controller interrogating the receiver processor module to determine its status (i.e., busy or available); and the bus controller then signaling transmission commencement.

Interprocessor communication

A multiprocessor system of the kind in which two or more separate processor modules are interconnected for parallel processing includes interprocessor buses dedicated exclusively to interprocessor communication. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time. An enable latch in each port dynamically disables that port from placing any signals on the related input/output bus in response to a failure of any portion of the device controller, and the enable latch is not responsive to the processor module for re-enabling the port. The device controller controls the transfer of information between a processor module and a peripheral device, and information is gated into a register in a port in a device controller in response to a gating signal generated by a processor module. Parity generation and check means continuously monitor parity for the duration of the gating signal.

Data error detection and device controller failure detection in an

A memory system for a computer detects data errors, address errors and operation errors to increase the reliability of data stored in the memory system. Address errors are detected by encoding address parity information into the data check field of each memory location. A signal is generated in each memory module indicating the status of operations of that memory module and is transmitted to the processor subsystem of the computer for comparison with a signal indicating the status of operations of the processor subsystem to insure that all memory modules and the memory control in the processor are receiving the same commands.

Memory system with operation error detection

In a multiprocessor system of the type in which two or more separate processor modules are connected by an interprocessor bus dedicated exclusively to interprocessor communication for parallel processing, there is provided an input/output system having multiported device controllers connected to the multiprocessor system by input/output buses. Each device controller is shared by pairs of the processor modules, and includes logic that ensures that only one port is selected for access at a time.

Multiprocessor system

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.

Power interlock system and method for use with multiprocessor systems

An input/output system for a processor of the kind in which a processor module has a central processing unit, a memory, an input/output channel, and a plurality of device controllers for controlling the transfer of data between the processor module and the peripheral devices includes a star poll connection in which each device controller is provided with a signalling means for signalling its identity in response to a poll operation, independently of other similarly connected device controllers such that any number of device controllers can be failed or powered off without affecting the polling of the other device controllers. The data lines in an input/output bus are used both to transmit data and to transmit signals to reduce the total number of lines needed to connect the device controllers to the channel in the star poll connection. The system is a fault tolerant system which includes an enable bit in the port of each device controller. The bit can be reset to prevent that device controller from transmitting spurious signals which could interfere with interrupt requests being transmitted to the channel by other device controllers so that a failed device controller can be effectively removed from the system. A rank line arrangement is utilized in the priority selection scheme so that an additional group of controllers can be added in a way which requires the use of only one more line in the input/output bus and still allows each device controller to respond independently to poll operations.

A datapath system and protocol is disclosed in which data is transferred between a computer memory and one or more peripheral devices through device controllers, each of which includes a buffer, through periodic connection of the device controller to the channel. The system and protocol are structured to permit multiple device controllers to cooperatively interact on a single channel, without direct communication between device controllers. Each device controller monitors the level of stress on its buffer and at appropriate times presents a reconnect request to the channel, together with indica for permitting the channel to determine the priority of a particular request relative to other reconnect requests. The times at which a reconnect signal should be presented are determined by monitoring the level of information storage in the buffer and relating that level to a threshold level; both overfilling and overemptying are prevented. The threshold level can be varied in accordance with a criteria which makes allowance for the number and combination of device controllers attached to the channel; and is set such that the remaining space in the buffer is sufficient to allow the buffer to transfer data to or from the associated peripheral device, at the rate demanded by that peripheral device, long enough to allow the channel to connect to one lower priority device controller, and all higher priority device controllers. The threshold level and buffer size are also set such that, after a reconnect, the buffer is capable of transferring data to or from the associated peripheral device, at the rate demanded by the peripheral, long enough for the channel to reconnect to all lower priority device controllers, to ensure that all device controllers, no matter the priority, are allowed access to the channel. The invention has broad application, but is particularly well-suited to fault tolerant computing systems.

Growing community of inventors

Sunnyvale, CA, United States of America

Steven W Wierenga