International Business Machines Corporation

Steven W Mittl

Anthony K Stamper

Chung H Lam

Karthick Rajamani

Eduard Albert Cartier

Alain F Loiseau

Charles Robert Lefurgy

Barry P Linder

Malcolm Scott Allen-Ware

Alan J Drake

Andreas Daniel Stricker

Thomas George Ference

Jay Sanford Burnham

Ronald Jay Bolam

Edward J Nowak

Terence B Hook

Matthew Joseph Breitwisch

Alvin Wayne Strong

Ernest Y Wu

Kimball M Watson

Ronald A Warren

Byron Lee Krauter

John M Aitken

Scott R Stiffler

David Erin Moran

Donald Lee Thompson

David G Brochu, Jr

Robert F Sechler

Timothy J O'Gorman

Dimitris P Ioannou

Travis S Merrill

Linda A Miller

Madhu Sayala

Timothy E Forhan

Jian W Zhu

Ernest Y Yu

Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Voltage balanced stacked clamp

Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.

Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.

Correction for stress induced leakage current in dielectric reliability evaluations

A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.

Monitoring aging of silicon in an integrated circuit device

A mechanism is provided for mitigating aging of a set of components in the data processing system. A modeled age of a component in the set of components is identified. A desired aging requirement for the component is identified and a determination is made as to whether the modeled age of the component is greater than the desired age of the component. Responsive to the modeled age of the component being greater than the desired age of the component, a policy is implemented to mitigate the aging of the component.

Managing aging of silicon in an integrated circuit device

A method establishes an initial voltage in a ring oscillator and a logic circuit of an integrated circuit device. Following this, the method enables the operating state of the ring oscillator. After enabling the operating state of the ring oscillator, the method steps up to a stressing voltage in the ring oscillator. The initial voltage is approximately one-half the stressing voltage. The stressing voltage creates operating-level stress within the ring oscillator. The method measures the operating-level frequency within the ring oscillator using an oscilloscope (after stepping up to the stressing voltage).

Measuring bias temperature instability induced ring oscillator frequency degradation

A reprogrammable integrated circuit (IC) including overwritable nonvolatile storage cells. Cell contents are compared in a differential sense amplifier against a variable reference signal that has a number of selectable reference levels corresponding to reprogrammed cell threshold voltages. With each write cycle the nonvolatile storage cells are overwritten and then, compared against a different, e.g., higher, selectable reference level.

Reprogrammable integrated circuit (IC) with overwritable nonvolatile storage

Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

Deuterium reservoirs and ingress paths

An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.

Electronic switch for decoupling capacitor

A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.

Silicon-on-insulator non-volatile random access memory device

A circuit actively monitors and measures the amount of MOS device degradation due to, for example, the hot electron effect, and makes compensatory adjustments to device voltage levels or clock speed to maintain desired levels of functionality and performance. Monitoring can be done separately for NFET and PFET devices to selectively adjust for different degradation rates between the two. In operation, the monitor circuit compares the performance of a stressed device to a reference device, that is, an unstressed device which has not been degraded by the hot-electron effect. The monitor circuit outputs a signal indicating the amount of device degradation. This signal is used to adjust the supply voltage to that device or to the chip or otherwise compensate for the degradation. The monitor circuit can be formed on-chip or off-chip.

Hot electron compensation for improved MOS transistor reliability

A method and system are provided for determining a guard band voltage differential for testing a microprocessor. The guard band voltage differential approximates microprocessor circuit propagation delay degradation expected to occur over the life of the microprocessor. The system and method are performed by first partitioning a microprocessor into a plurality of cones of n circuit level models. Timing simulation data and degradation data are created to represent, respectively, the timing operation for each of the circuit level model circuit paths, and the hot-electron effects on propagation delay degradation for each of the circuit level models. Propagation delay is identified using this data for each of the circuit paths for the circuit level models at times corresponding to the beginning-of-life and end-of-life of the microprocessor. Propagation delay degradation is calculated as the difference between the propagation delay at these times. A range of applied power supply voltages necessary to successfully perform a functional test of the microprocessor over a corresponding range of microprocessor cycle times is experimentally determined. Based on the calculated propagation delay degradation and on the range of applied power supply voltages, a guard band voltage differential for testing the microprocessor is determined.

Method to calculate hot-electron test voltage differential for assessing

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Steven W Mittl