Juniper Networks, Inc.

Marvell Asia Pte., Ltd.

Sun Microsystems, Inc.

Cavium, Inc.

Steven W Aiken

Srihari Raju Vegesna

Craig R Frink

Gerald Lampert

Wilson Parkhurst Snyder, Ii

Jason Daniel Zebchuk

David Albert Carlson

John A Saba

Thomas J Meyer

Ajit Jain

A system and corresponding method isolate work within a virtualized scheduler using tag-spaces. The system comprises a tag-space resource configured to store at least one respective assignment of at least one scheduling group to a given tag-space. The given tag-space defines a given ordering-atomicity domain that isolates, within the virtualized scheduler, (i) work belonging to the at least one scheduling group from (ii) work belonging to at least one other scheduling group, assigned, in the tag-space resource, to a respective tag-space different from the given tag-space. The system further comprises a work scheduler that schedules, for processing, work belonging to the at least one scheduling group and work belonging to the at least one other scheduling group. Such scheduling may have independent ordering and atomicity effectuated therebetween by the given ordering-atomicity domain. Such independency of ordering and atomicity improves quality-of-service of the virtualized scheduler.

System and method for isolating work within a virtualized scheduler using tag-spaces

In some embodiments, an apparatus includes a transmission schedule module in at least one of a memory or a processing device that can select, at a first time, a data unit to send to a network device based at least in part on a value of a transmission rate counter indicating that the network is in a first state. The transmission schedule module can receive, at a second time, an indication of a number of buffers associated with the data unit and can calculate a size estimate of the data unit based on the number of buffers and a capacity associated with each buffer. The transmission schedule module can calculate at a third time, a temporary transmission rate count and can send a signal to transition the network device from the first state to a second state if the temporary transmission rate count meets a criterion.

Methods and apparatus for scheduling transmission of data in a network

An apparatus for increasing scheduling efficiency in network devices may include (1) at least one memory device that stores at least one data chunk included in a packet, (2) a scheduler device that (a) schedules transmission of the packet that includes the data chunk and (b) issues a request to transmit the packet based at least in part on the scheduled transmission, and (3) a packet-delivery device that (a) receives the request to transmit the packet from the scheduler device, (b) prepares the packet for transmission at a faster rate than the scheduler device schedules the transmission of the packet, and then (c) facilitates transmitting the data chunk included in the packet to a computing device. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for increasing scheduling efficiency in network devices

In an example embodiment, a method may include collecting, at a controller within an integrated circuit, defect information indicative of defects identified during a built-in self-test (BIST) operation performed on plural memories embedded within the integrated circuit. Fuses within the integrated circuit may be blown based on the defect information collected automatically and without software intervention. The fuses blown may be used to inform a built-in self-repair (BISR) operation performed on the plural memories.

Auto-blow memory repair

An interface for transferring data via a PCI bus between a initiator device and a host target having a local cache buffer. The PCI interface to the local cache buffer includes an interface controller, an address resolution unit, data and address logic, byte enable logic and command processing logic. The command and data logics resolve address hits and misses and determine when a write operation will occur to the local cache buffer. The interface controller performs hand shaking operations between the PCI interface and an initiator device connected via the PCI bus. The interface controller also regulates the transfer of data between the device initiator and the local cache buffer, providing status and control signals to the cache controller during a given transfer cycle. The data logic receives the data from the PCI bus and verifies parity providing data and parity information to the cache buffer and cache parity error buffer. The byte enable logic receives and processes byte enable information associated with each data transfer phase and generates start pointer and end pointer information for a determination of the valid data bytes which are stored in a particular cache line. Finally, the interface controller generates an end of line signal upon the completion of a cache line write allowing for the transfer of uniform data blocks across the cache buffer to host boundary.

Growing community of inventors

Pepperell, MA, United States of America

Steven W Aiken