Seagate Technology Incorporated

Steven V Holsinger

Vadim B Minuhin

Vladimir Kovner

Stephen R Genheimer

Srinivasan Surendran

Shafaollah Dahandeh

Method and apparatus for controlling the timing of the sampling of signals and signal amplitude in a PRML read channel. A VCO generates a read clock and a clock generator connected to the VCO generates even and odd clock signals corresponding to even and odd cycles of operation of the VCO. Serially connected even sample and hold circuits respond to clock signals to store samples of the read channel signal taken during successive odd cycles and serially connected odd sample and hold circuits store samples taken during successive even cycles. Comparator circuits compare the samples taken in each cycle to reference signals and the comparisons are clocked through two stage, even and odd shift registers to provide estimates of the presence or absence of nonzero samples for each even and odd cycle. Even and odd time error generators connected to the sample and hold circuits and, via AND gates enabled during even and odd cycles respectively, to the shift registers, generate even and odd time error signals from the samples and estimates during even and odd cycles respectively. An adder transmits the even and odd time error signals to the VCO input. Even and odd gain error generators connected to the sample and hold circuits and the AND gates generate even and odd gain error signals transmitted to a variable gain amplifier in the read channel.

Timing and gain control circuit for a PRML read channel

A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences. Each Viterbi decoder includes an analog adder and an analog subtracter for generating the sums and differences of each sample and a reference signal, a sample and hold circuit codected to the adder and subtracter to receive the sums and differences, a difference circuit that generates the difference between the contents of the sample and hold circuit and each sample, a comparator assembly that generates a two bit merge indicator signal from the output of the difference circuit and the reference signal, AND gates that transmit bits of the indicator signal to switches in the sample and hold circuit for entering the sum or difference of the sample and reference signal into the sample and hold circuit, a shift register having interstate decoders that transmit logical 1's in response to a specific nonzero bit of the merge indicator signal and an indicator bit while otherwise transmitting a logic value determined by the logic value received from a preceding stage of the shift register and a pointer for generating indicator bits for each sample for which the merge indicator signal is logical 00.

Maximum likelihood detector for a disc drive PRML read channel

A prewrite compensation circuit for use with a hard disk drive wherein surfaces of disks of the drive are formatted for writing data to the surfaces at different frequencies selected for different concentric zones on the surface. Data to be written is passed through a shift register to a series of delay elements and a multiplexer that passes the output of a delay element selected in relation to a data word received by the multiplexer to a write circuit that writes the data to the disc. The delay words, or elements of delay words, are stored in latches that are selectively connected to the multiplexer, or a delay word accumulator connected to the multiplexer, in relation to the pattern of bits surrounding a bit to be written. A delay calibration circuit includes an inverter and a timing circuit that connects the inverter across the delay elements, or a series of delay elements having the same electrical characteristics, for a series of time intervals prior to writing to a new zone to form a ring oscillator whose oscillations clock a counter during each time interval. Following each time interval, the counter contents are entered into a selected latch.

Adaptive prewrite compensation apparatus and method

An apparatus for providing sector location pulses to a controller of a rotating disk data storage device having a counter clocked in proportion to the disk rotation rate and an accumulator for accumulating times to sectors on the disk. A comparator connected to the counter and the accumulator enables an accumulator clock for repetitive clocking of the accumulator at such times the contents of the accumulator do not exceed the contents of the counter. A sector location pulse generator connected to the comparator generates the controller pulses, when enabled, concurrently with the accumulator clock signals. A master reset generator resets the first counter and the accumulator each time an index location on the disk passes a transducer head used to read and write data to and from the disk and a partial reset generator resets the accumulator each time the transducer head is moved between tracks on the disk. The sector location pulse generator includes a flip-flop that is set following a partial reset signal to prevent sector location pulses from being generated following partial reset until the accumulator has accumulated the count in the counter.

Hard sectoring circuit and method for a rotating disk data storage device

An adaptive prewrite compensation apparatus for writing data flux transition data on a magnetic medium, the apparatus incorporated in a disk drive assembly. A serial data pattern is introduced into the apparatus from a drive interface in digital form and is encoded. A combination of a transducing head and a writing location used for writing the data pattern on the magnetic medium is determined by the assembly. A predetermined write delay value based on the combination and the data pattern is computed by the assembly which then writes the data pattern on the magnetic medium with reference to the write delay value so that when the data pattern is read back, the flux transitions are preceived to be at the same distance as when entered into the apparatus.

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Oklahoma City, OK, United States of America

Steven V Holsinger