Imec

Interuniversitair Microelektronica Centrum (imec)

Infineon Technologies Ag

Imec Vzw

Sofics Bvba

Hanwa Electronics Ind. Co. Ltd.

Steven Thijs

Dimitri Linten

Natarajan Mahadeva Iyer

Christian Cornelius Russ

Benjamin Van Camp

Olivier Marichal

Mirko Scholz

Vincent De Heyn

Gerd Vermont

David Eric Trémouilles

Vesselin K Vassilev

Pieter Vanysacker

Wybo Geert

David Trémouilles

Tom Daenen

An distributed electronic circuit (), such as a transmission line or distributed amplifier, is disclosed comprising an input terminal (), an output terminal (), power supply lines (), a sequence of sections (), between the input terminal () and the output terminal (), arranged to transfer an electrical signal from one section to another section; each section () comprising at least one Electro Static Discharge (ESD) protection component () configured to, upon occurrence of an ESD event, convey corresponding ESD currents to a power supply line (); and wherein the ESD components () of the respective sections () are selected such that, upon occurrence of an ESD event, at least one subsequent section () is triggered before the first section ().

Method for providing wideband electrostatic discharge protection and circuits obtained therewith

The present invention provides an electrostatic discharge (ESD) protection circuit with a silicon controlled rectifier (SCR) having a plurality of SCR fingers (SCRs) with the advantages to couple the different fingers or SCRs to decrease the multi-triggering problem and to increase the ESD-performance of the circuit. Additionally, a boost circuit can be introduced or additionally multiple SCRs can be coupled inherent through a common base.

Electrostatic discharge protection circuit

A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (W), gate length (L) and number of fins (N) on the basis of the optimum value; and manufacturing said MuGFET ESD protection device using the given manufacturing and process values.

Design methodology for MuGFET ESD protection devices

The present disclosure relates to a method for calibrating transient behaviour of an electrostatic discharge (ESD) test system. The system includes an ESD pulse generator and probe needles for applying a predetermined pulse on a device under test. The probe needles are connected to the ESD pulse generator via conductors. The test system includes measurement equipment for detecting transient behaviour of the device under test by simultaneously capturing voltage and current waveforms the device as a result of the pulse. The method includes the steps of: (a) applying the ESD test system on a first known system with a first known impedance, (b) applying the ESD test system on a second known system with a known second impedance, and (c) determining calibration data for the transient behaviour the ESD test system on the basis of captured voltage and current waveforms, taking into account said known first and second impedances. In preferred embodiments the waveforms are transferred to the frequency domain for correlation.

Method for calibrating an electrostatic discharge tester

An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.

Electronic circuit and method of manufacturing an electronic circuit

A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.

Electrostatic discharge protected circuits

A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.

Method of determining current-voltage characteristics of a device

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Willebroek, Belgium

Steven Thijs