Sandisk Technologies Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Sun Microsystems, Inc.

Sandisk Enterprise IP LLC

Steven Theodore Sprouse

Yan Li

Chris Avila

Sergey Anatolievich Gorobets

Jianmin Huang

Nian Niles Yang

Dhaval Parikh

Yichao Huang

William S Wu

James M Higgins

Neil David Hutchison

Patricio Collantes

Ka Ian Yung

Alan David Bennett

Robert C Miller

Chris Nga Yee Avila

Satish Babu Vasudeva

Jian Feng Chen

Dana Lee

Aaron Keith Olbrich

Suresh Kumar Upadhyayula

Neil Richard Darragh

Yingda Dong

Hem P Takiar

Gerrit Jan Hemink

Robert W Ellis

Jun Wan

Abhijeet Manohar

Xinde Hu

Bo Lei

Uday Chandrasekhar

Shai Traister

Navneeth Kankani

Johann George

Alexander Kwok-Tung Mak

Reed P Tidwell

Emilio Yero

Xinmiao Zhang

Alexandra Bauche

Rodney Brittner

Zac Shepard

Marielle Bundukin

Jonathan Q Tu

Shakeel I Bukhari

Masaaki Higashitani

Johann Alsmeier

Deepanshu Dutta

Yanli Zhang

James Fitzpatrick

Seungpil Lee

Michael J McCarthy

Kroum Stanimirov Stoev

Seungjune Jeon

Kulachet Tanpairoj

Liam Michael Parker

Carlos J Gonzalez

Aaron Lee

Zhixin Cui

Akio Nishida

Tien-Chien Kuo

Ishai Ilani

Ron Barzilai

Philip David Reusswig

Lee M Gavens

Alex Mak

Alan Lee Winick

David George Dreyer

Arjun Kapoor

John Richard Busch

Michael T Milo

Frank Tsai

Ameen Aslam

Sukhminder Singh Lobana

Mark David Myran

Ryan Takafuji

Tienchien Kuo

Neil David Hutchinson

Meiman Lin Syu

Nathan Rapaport

Ryan Marlin

Tom Hugh Shippey

Yauheni Yaromenka

Neil R Darragh

Jr Patricio Collantes

A data storage device is configured to store a database of objects in an NVM die as binary vectors and to then search the database based on binary key vectors. The binary vectors may be received from a host for storage in the NVM die. In other examples, a data storage controller converts floating-point vectors received from the host into binary vectors for storage in the NVM die. Various procedures are described for converting the floating-point vectors into binary vectors. Exemplary procedures are also described for comparing a binary key vector received from the host with the binary vectors stored in the NVM die to detect matches. For example, a sequence of commands is described for applying by the data storage controller to the NVM die to control the die to identify and count matching bits using the latches of the NVM die. Volatile memory implementations are also described.

Memory die with on-chip binary vector database search

Systems, methods and/or devices are used to enable locality grouping during garbage collection of a storage device. In one aspect, the method includes, at a storage controller for the storage device: performing one or more operations for a garbage collection read, including: identifying one or more sequences of valid data in a source unit, wherein each identified sequence of valid data has a length selected from a set of predefined lengths; and for each respective sequence, transferring the respective sequence to a respective queue of a plurality of queues, in accordance with the length of the respective sequence; and setting a global flag to flush all open queues; and performing one or more operations for a garbage collection write, including: identifying open respective queues for writing to a destination unit; and writing from the open respective queues to the destination unit.

Locality grouping during garbage collection with flush of buffered write data upon completion of garbage collection operation

A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.

Bonded assembly containing memory die bonded to integrated peripheral and system die and methods for making the same

Systems, methods and/or devices are used to enable locality grouping during garbage collection of a storage device. In one aspect, the method includes, at a storage controller for the storage device: performing one or more operations for a garbage collection read, including: identifying one or more sequences of valid data in a source unit, wherein each identified sequence of valid data has a length selected from a set of predefined lengths; and for each respective sequence of the one or more sequences of valid data in the source unit, transferring the respective sequence to a respective queue of a plurality of queues, in accordance with the length of the respective sequence; and performing one or more operations for a garbage collection write, including: identifying full respective queues for writing to a destination unit; and writing from the full respective queues to the destination unit.

Locality grouping during garbage collection of a storage device

In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, determines a backlog of the respective channel controller in accordance with pending commands in one or more command queues, receives power credits allocated by the storage controller, based at least in part on the backlog of the respective channel controller, and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received power credits. For example, limiting execution includes deferring execution of a respective command in accordance with a determination that executing the respective command would require power credits in excess of power credits available in the respective channel controller.

Distributed power management for non-volatile memory controllers

In a memory system having a storage controller and a plurality of distinct sets of non-volatile memory devices, each respective channel controller of a plurality of channel controllers, each channel controller corresponding to a distinct set of the plurality of distinct sets of non-volatile memory devices, receives power credits allocated by the storage controller, including an average power credit and a peak power credit; and while executing commands in the one or more command queues, limits execution of said commands in accordance with the received average power credit and the received peak power credit. In some embodiments, a total number of average power credits allocated by the storage controller is variable and a total number of peak power credits allocated by the storage controller is fixed.

Distributed power management for non-volatile memory controllers using average and peak power credits allocated to memory channels

The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.

Scaling large drives using enhanced DRAM ECC

A set of superblocks can be constructed by a memory controller employing good blocks and partially bad blocks in a plurality of memory access units. Each functional memory access unit among the plurality of memory access units contributes a single block that is a good block or a partially bad block to each superblock. The memory controller can further construct a set of super word line zones within each superblock in the set of superblocks. Each block within a superblock contributes a good word line zone to each super word line zone. Upon encounter of a program error at run time, the super word line zones within the superblock may be modified to continue running the program employing modified super word line zones for the superblock.

System and method for implementing super word line zones in a memory device

In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.

Erasure correcting coding using temporary erasure data

In an illustrative example, a method includes receiving data that includes a set of data symbols. The method further includes generating a set of parity symbols based on the set of data symbols using an erasure correcting code. The set of parity symbols includes at least a first parity symbol that is generated based on a first proper subset of the set of data symbols. The first parity symbol enables recovery of a data symbol of the first proper subset independently of a second proper subset of the set of data symbols.

Erasure correcting coding using data subsets and partial parity symbols

A NAND Flash based content addressable memory (CAM) is used for a key-value addressed storage drive. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. A host writes a key-value pair to the drive, where the drive writes the keys along bit lines of a CAM NAND portion of the drive and stores the value in the drive. The drive then maintains a table linking the keys to location of the value. In a read process, the host provides a key to drive, which then broadcasts down the word lines of blocks storing the keys. Based on any matching bit lines, the tables can then be used to retrieve and supply the corresponding data to the host.

Key value addressed storage drive using NAND flash based content addressable memory

Systems, methods and or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.

Method for improving mixed random performance in low queue depth workloads

A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line.

Method and system for dynamic word line based configuration of a three-dimensional memory device

A method of scheduling memory operations to be performed by non-volatile memory devices in a storage system includes identifying a plurality of memory operations to be performed by a plurality of non-volatile memory devices in the storage system. The number of memory operations in the plurality of memory operations is no greater than the number of non-volatile memory devices in the plurality of non-volatile memory devices; each memory operation is to be performed by a distinct non-volatile memory device; and the memory operations include host writes, garbage collection writes, and garbage collection reads. The method also includes, for each non-volatile memory device, assigning preference values to each of the memory operations. The method further includes assigning each memory operation to a distinct non-volatile memory device, using the preference values assigned to each of the memory operations for each non-volatile memory device.

Scheduling operations in non-volatile memory devices using preference values

The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Method for modifying device-specific variable error correction settings

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San Jose, CA, United States of America

Steven Theodore Sprouse