Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Hewlett-packard Corporation

Steven T Mangelsdorf

Gregg Bernard Lesartre

Russell C Brockmann

Douglas Benson Hunt

Gregory L Ranson

David V James

Patrick Knebel

Jonathan P Lotz

John William Bockhaus

Paul L Perez

Russell W Mason

Robert E Naas

A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin a test program in the uncommitted state. When the random code generator is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Testing a processor using a random code generator

A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the register value is committed to that value at that point. Uncommitted values can propagate through one or more previous instructions. All registers and memory begin the test program in the uncommitted state. When the random code generators is done generating the test program, if any uncommitted values remain, then the uncommitted values are committed to arbitrary values.

Management of uncommitted register values during random program generation

Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached. A scoring function is used to prioritize which logic gate and which nodes are to be selected for code generation. Tri-state buffers are simulated using boolean operations. Drive-fight checking is also accomplished using boolean operations.

Method of reducing boolean complements in code generated by a circuit

Method of processing information in a microprocessor. At a first time during the life cycle of an instruction, a first set of microprocessor self-monitoring information is generated. The first set of mnicroprocessor self-monitoring information is stored, information necessary to execute the instruction is stored, and the two are associated. At a second time during the life cycle of the instruction, a second set of microprocessor self-monitoring information may be generated. This is also stored and is associated with the information necessary to execute the instruction. If the instruction retires, the first and second information may be retrieved for use in microprocessor testing. The information may also be used as soon as it is generated, for example by communicating the information itself or indicators derived from it to a state machine configured to facilitate microprocessor testing. The invention may also include a method of processing information in a microprocessor to facilitate microprocessor testing operations, wherein system bus monitoring information is generated whenever system bus accesses occur. This information, or indicators derived from it, is communicated to a microprocessor testing state machine on-chip with the microprocessor. In yet other embodiments, the invention may include the steps of: generating microprocessor self-monitoring information at various times during the life cycle of an instruction; utilizing the microprocessor self-monitoring information both when it becomes available as well as later, after retirement of the associated instruction; generating system bus monitoring information whenever system bus accesses occur; and utilizing the system bus monitoring information when it becomes available.

Method for processing information in a microprocessor to facilitate

Method of improving store efficiency and memory allocation in code

Method of efficiently modeling tri-state gates

Method of efficiently displacing register contents in code generated by

Method of selecting gates for efficient code generation by a circuit

Method of producing cache optimized code from a circuit compiler

Aliasing nodes to improve the code generated by a circuit compiler

Method of producing simplified code from a circuit compiler

User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements. By changing data in the storage elements, the programmer may change the information against which the state of the nodes is compared and also the method by which the comparison is made. The output devices include counters. Counter outputs may be used as state machine inputs, so one event may be defined as a function of a different event having occurred a certain number of times. The output devices also include circuitry for generating internal and external triggers. User-configurable multiplexer circuitry may be used to route user-selectable signals from within the microprocessor to the chip's output pads, and to select various internal signals to be used as state machine inputs.

System and method for on-chip debug support and performance monitoring

Method of eliminating unnecessary code generation in a circuit compiler

A floating point processor in which floating point register file write enables are self-timed from the exception flags from the respective floating point processing units. This self-timing is achieved by forming the floating point processing units from self-timed logic gates which gate data in accordance with the values of the data itself. In other words, the output of a logic gate is made valid only when all inputs to the logic gate have been evaluated as being valid. Since the floating point exception signals from the floating point processing units are also self-timed and no longer edge triggered, the results of the floating point operation may be written to the register file on the same phase in which the result and the exception flags become valid, thereby allowing processing latency to be reduced by a state. Hence, if there is a floating point exception during a floating point operation, the register cell is not written. The floating point exception flags are also precharged to a true level and remain true until it is conclusively determined that a floating point exception will not result from the current floating point operation. At that time, the register cell is immediately written.

Qualification of register file write enables using self-timed floating

Disclosed is a data bus synchronizer circuit based on the principle that if the phase relationship of a sending bus clock and a receiving bus clock is known at a first point in time, and the frequencies of the two clocks are known and fixed, then the phase relationship can be determined at any time in the future through extrapolation. The circuit has a pipe, used to remove metastability from the sending bus clock, comprising a plurality of flip-flop circuits connected in series. The clock of the sending bus is input to the first flip-flop of the pipe, and the pipe flip-flop circuits are clocked by the receiving bus clock. Because the extrapolation principle, the pipe can be arbitrarily long. Output of this pipe is fed to the input of a serial to parallel conversion circuit comprising a second group of flip-flop circuits connected in series, and clocked by the receiving bus clock. The parallel outputs of the converter are fed to selector circuits, with the desired adjacent parallel outputs being selected by programming bits which allow the circuit to be adapted to varying ratios of sending and receiving clock speeds. The outputs of the selector circuits are fed to an AND gate that creates an enabling signal that is used to enable the transfer. The circuit allows a transfer even where one of the bus cycles is more than twice as long as the other bus cycle, and the circuit takes advantage of bus setup time to speed up data transfers.

Synchronizer using clock phase extrapolation

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Fort Collins, CO, United States of America

Steven T Mangelsdorf