Unisys Corporation

L-3 Communications Corporation

Steven T Barham

Samuel Charles Kingston

Harold L Simonsen

Ronald S Leahy

Robert W Steagall

Thomas R Giallorenzi

Raied N Mazahreh

Alan E Lundquist

Randal R Sylvester

Zachary C Bagley

Patrick J Smith

W Paul Willes

Michael J Hurst

Zackary C Bagley

John W Zscheile, Jr

Merle LeRoy Keller, Jr

DeLon K Jones

Lyman D Horne

Warren Paul Willes

John W Love

Mark C Austin

Harold L Simonson

Sharen Wirkus

Charles A Small

Steven J McEntire

A digital communication system includes a generator for generating a plurality of pulse trains, each having a different timing, and pre-compensation circuitry for synchronizing the plurality of pulse trains to a timing signal. The system also includes comparison circuitry for simultaneously comparing a received burst code signal to each of the plurality of pulse trains, where the burst code signal is synchronized to the timing signal, and a detector for detecting which of the pulse trains is a closest temporal match to the burst code signal. The pre-compensation circuitry operates to reduce acquisition time and keep PN code uncertainties within the range of the comparison circuitry.

Acquisition and tracking of burst code signals

An apparatus and method of determining a signal code. The method comprising steps of acquiring and correlating a signal with a first code sequence. In response to the timing lock is achieved. Also in response to the signal correlation, an acknowledge from a receiver of the signal to a transmitter change to a second code sequence.

Apparatus for rapid PN code acquisition

An apparatus and method of determining a signal code. The method comprising steps of acquiring and correlating a signal with a first code sequence. In response to the correlation of the signal with a first code sequence a timing lock is achieved. Also in response to the signal correlation, an acknowledgement from a receiver of the signal to a transmitter of the signal is sent where upon the receiver and transmitter change to a second code sequence.

Apparatus for rapid PN code acquistion

A high speed demodulator system is comprised of an analog to digital converter (ADC); a high speed demultiplexer connected to an input of the ADC; a bank of parallel programmable demodulators connected to an output of the high speed demultiplexer; a timing interface connected to the bank of parallel programmable demodulators; and a phase reference interface connected to the bank of parallel programmable demodulators and a data processor. A parallel programmable demodulator includes a reconfigurable FIR filter, has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The programmable FIR filter provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

One sample per symbol high rate programmable parallel architecture for digital demodulation

An integrated circuit includes a reconfigurable FIR filter has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a sequential weight processor having an input coupled to an output of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.

Rapid acquisition dispersive channel receiver integrated circuit

Users or subscribers of a spread spectrum synchronous communications system provide signals to the central station or base unit of that system, and receive signals therefrom. Proper synchronization among those users (and their signals) is needed to ensure proper operation of the system. To ensure proper synchronization among those users, the signal produced by each user is checked for presence and amount of any offset error. This is accomplished by using three despreaders for the signal for each user. For one such user, each such despreader for that user receives the spreading code for that user. However, the spreading code as received by any one such despreader is time-delayed with respect to the spreading code as received by the other two despreaders. Each such despreader receives the spreading code with a different amount of delay imposed on that spreading code. The outputs of the three despreaders are digitally combined (e.g. compared), or compared, to produce the offset estimate for that user. To reduce noise effects, the offset estimate is averaged over a predetermined time duration; alternatively, such averaging can be performed on the outputs of the despreaders, or at some intermediate processing step. The offset estimate is sent to the user, to be used to correct synchronization of that user. Offset estimates that are too small to be useful are squelched and are not so sent to the user, to reduce channel usage and thereby save bandwidth.

Synchronizer and method therefor and communications system incorporating same

Apparatus and method for digital frequency discrimination are provided that only require one sample per data symbol (e.g. one bit for BPSK or 2 bits for QPSK). This is accomplished by determining the difference between the carrier phase error on successive data symbols. The difference in phase error is then used as an approximation to the derivative of the phase error, which is the frequency error between the carrier and the local oscillator of the receiver. An important advantage of this apparatus and method is that they allow the maximum symbol rate to be processed by the receiver for a given digital technology. In other words, maximum symbol rate can now be equal to the maximum clock rate of the digital technology, if so desired by the user. In contrast, conventional digital frequency discriminators limit the maximum symbol rate to one-half or one-fourth of the maximum clock rate for a given digital technology. A key feature is the use of a threshold apparatus and method that allows the discriminator to ignore phase shifts that are due to data modulation, and only use phase shifts that are due to carrier frequency errors. Thus, when successive data symbols are identical, frequency error information can be obtained for carrier recovery. When successive data symbols are different, no updates are made to the carrier recovery. This allows a carrier recovery loop to operate at a rate of one sample per data symbol.

Frequency discriminator and method and receiver incorporating same

Apparatus and method are provided that can be advantageously included in a timing phase-locked loop for finally adjusting the period of a timing signal being controlled by that loop. The loop filter receives the timing signal and generates a loop error signal indicative of whether the period of the timing signal should be held the same, increased or decreased. A strobe signal is also generated each time that the timing signal is to be so corrected. The error signal and strobe signal are provided to a function generator such as a state machine. Each time that the function generator is strobed by the strobe signal, it produces a count signal whose value is representative of N, N+C or N-C, where N and C are integers and C represents a preset desired increment of change for the timing signal per strobe, i.e. the fineness of the adjustment of the timing signal. When not strobed by the strobe signal, the state machine produces a count signal of value N. When the state machine is strobed by the strobe signal and the error signal indicates that the timing signal should be held as is, the state machine remains in a first state such that the count signal has a value of N. If the state machine is strobed by the strobe signal and the error signal indicates that the period of the timing signal should be increased, then the state machine moves to a second state such that a digital count signal of N+C is generated once, after which the state machine returns to the first state. If the state machine is strobed by the strobe signal and the error signal indicates that the period of the timing signal should be decreased, then the state machine is moved to a third state such that a digital count signal of N-C is produced once, after which the state machine returns to the first state. The count signal is provided in parallel to a divide-by counter, which also receives a clock signal having a fixed frequency N times the frequency of the timing signal. The counter divides the clock signal by the value of the count signal to produce the timing signal. This timing signal is provided to the loop filter. The timing signal can also be used for example to clock in data.

Variable rate clock for timing recovery and method therefor

Synchronizer and method therefor and communications system incorporating

In a spread spectrum multipoint-to-point communication system there is provided a novel frequency to phase converter, for automatically synchronizing the PN codes of the user transmitters/receiver with the receiver/transmitter in the central hub. The highly accurate frequency to phase converter generates a highly accurate phase error signal for synchronizing the multiuser network. The frequency to phase converter includes a serial adder and a series to parallel converter and a shift register which integrates the highly accurate phase error signal values and produces a highly accurate frequency value which is applied to the input of the resident processor in the central hub transmitter/receiver. The central hub transmitter/receiver calculates the clock offset for synchronizing each of the user receiver transmitters and generates a clock adjusting signal which is transmitted to the user receiver/transmitters.

Apparatus for synchronizing multipoint-to-point communications systems

An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of '1' and '0' chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of '1' chips minus the number of '0' chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.

Electronic transmitter having a digital combiner circuit for

A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed to produce an epoch signal when the transmitted carrier frequency and/or chipping rate is varied in a pseudorandom manner and is coupled to the timing controls so that the modulator replicates the received variable rate signals.

Programmable randomly tunable digital demodulator

A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.

Parallel processing based digital matched filter and error detector for

An interface for coupling a standard telephone set to a distributed digital network for allowing digital voice communication over the distributed network such that the utilization of the distributed network is wholly transparent to the user. An interface is provided for each telephone set. Each interface includes a state machine, a coder/decoder and a digital tone generator. The state machine is responsive to analog control signals from the telephone set to generate digital control signals to be transmitted over the distributed network. The state machine is also responsive to digital control signals to control the digital waveform generator to generate supervisory tones which are relayed to the user by the telephone set. The state machine also monitors the operation of the corresponding state machine or machines in a normal or conference call and sends control signals to resolve inconsistent states of the respective state machines, resulting in a high degree of fault tolerance and independence from network protocols.

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Salt Lake City, UT, United States of America

Steven T Barham