Taiwan Semiconductor Manufacturing Comp. Ltd.

Steven Swei

Tien-Chun Yang

Chan-Hong Chern

Ming-Chieh Huang

Chih-Chang Lin

David Barry Scott

Some embodiments regard a circuit comprising: a first circuit configured to lock a frequency of an output clock to a frequency of a reference clock; a second circuit configured to align an input signal to a phase clock of the output clock; a third circuit configured to use a first set of phase clocks of the output clock and a second set of phase clocks of the output clock to improve alignment of the input signal to the phase clock of the output clock; and a lock detection circuit configured to turn on the first circuit when the frequency of the output clock is not locked to the frequency of the reference clock; and to turn off the first circuit and to turn on the second circuit and the third circuit when the frequency of the output clock is locked to the frequency of the reference clock.

Phase-lock assistant circuitry

A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output.

Voltage reference circuit with temperature compensation

An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Integrated circuits including a charge pump circuit and operating methods thereof

A circuit includes a comparator, a first circuit, and a second circuit. The comparator has a first input node and a second input node. The first circuit is configured to output a temperature-dependent voltage at the first input node of the comparator. The first circuit includes a current mirror configured to generate a first reference voltage. The second circuit is configured to output a second reference voltage at the second input node of the comparator responsive to a digital code and the first reference voltage.

Temperature sensing circuit

A thermal sensor includes a comparator having a first and second input nodes. A reference voltage generator is electrically coupled with the first input node. The reference voltage generator is configured to provide a reference voltage that is substantially temperature-independent. A temperature sensing circuit is electrically coupled with the second input node. The temperature sensing circuit is configured to provide a temperature-dependent voltage. The temperature sensing circuit includes a current mirror. A first metal-oxide-semiconductor (MOS) transistor is electrically coupled between the current mirror and ground. A first resistor is electrically coupled with the current mirror. A second MOS transistor is electrically coupled with the first resistor in series. The second MOS transistor and the first resistor are electrically coupled with the first MOS transistor in a parallel fashion.

Thermal sensors and methods of operating thereof

A memory circuit including at least one memory array and at least one sleep transistor connected to the at least one memory array and connected to a first power line for providing a first power voltage. The memory circuit further includes at least one diode-connected transistor directly connected to the at least one memory array and directly connected to the first power line and a back-bias circuit electrically coupled with a bulk of the at least one diode-connected transistor.

Memory circuits having a diode-connected transistor with back-biased control

A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45&#xb0; phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Method of operating phase-lock assistant circuitry

A voltage reference circuit with temperature compensation includes a power supply, a reference voltage supply, a first PMOS transistor with its source connected to the power supply voltage, a second PMOS transistor with its source connected to the power supply and its gate and drain connected to the first PMOS gate, a first NMOS transistor with its gate and drain connected the first PMOS drain, a second NMOS transistor with its drain connected to the second PMOS drain and its gate connected with the first NMOS gate to the reference voltage supply, a resistor connected to the second NMOS source and ground, and an op-amp with its inverting input and its output connected the first NMOS source and its non-inverting input connected to the ground. In another aspect, a voltage reference circuit output is coupled to an NMOS gate in saturation mode connected to another voltage reference circuit.

Mechanisms for providing linear relationship between temperatures and digital codes are disclosed. In one method, at a particular temperature, a circuit in the sensor provides a temperature dependent reference voltage, and a compared voltage, to a comparator. The temperature dependent reference voltage depends on temperature in complement to absolute temperature or alternatively depends on temperature in proportion to absolute temperature. The compared voltage is generated corresponding to digital analog converter (DAC) codes as inputs. Another circuit varies the DAC codes until the temperature dependent reference voltage and the compared voltage are equal so that the dependent reference voltage corresponds to a DAC code. The various temperatures experienced by the temperature sensing circuit and the DAC codes are substantially linearly related.

Providing linear relationship between temperature and digital code

A memory circuit includes at least one memory array. At least one sleep transistor is electrically coupled between the at least one memory array and a first power line for providing a first power voltage. At least one diode-connected transistor is electrically coupled between the at least one memory array and the first power line. A back-bias circuit is electrically coupled with a bulk of the at least one diode-connected transistor.

A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C) and a second counter (e.g., counter C), which, together with the first counter C, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter Ccounts, e.g., to N, and counter Ccounts to Nwhere N=N+N. For counter Cto count to N, Nis loaded to counter C. Similarly, for counter Cto count to N, Nis loaded to counter C. While counter Ccounts (e.g., to N), Ncan be loaded to counter C. After counter Cfinishes counting to N, N, if loaded, is available for counter Cto start counting to this N. Counters Cand Ccan alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.

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Fremont, CA, United States of America

Steven Swei