Advanced Micro Devices Corporation

Steven Shyu

David L Campbell

Jiu An

Jimmy Fung

In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

Switchable DAC with current surge protection

A pipeline memory access circuit has a memory address buffer for buffering memory addresses. The buffer has a first and a second pass gate, and each of the pass gates has a pair of complementary metal-oxide-semiconductor (CMOS) transistors. An apparatus is provided for selectively switching the buffer between an asynchronous and a synchronous mode of operation. The switching apparatus includes circuits for alternately opening and closing the first and second pass gates when the buffer is in its synchronous mode of operation and for simultaneously opening both of the pass gates when the buffer is in its asynchronous mode of operation.

Asynchronous/synchronous pipeline dual mode memory access circuit and

In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.

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Cupertino, CA, United States of America

Steven Shyu