Lsi Logic Corporation

Lsi Corporation

Goke US Research Laboratory

Steven Schauer

Christopher D Paulson

Timothy D Thompson

Engling Yeo

Xinhai Kang

David L Schell

Kevin Campbell

A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Method and apparatus for data compression and decompression using a standardized data storage and retrieval protocol

A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Method and apparatus for data encoding and decoding using a standardized data storage and retrieval protocol

A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Method and apparatus for data encryption using a standardized data storage and retrieval protocol

Apparatus, circuits, systems, and associated methods for integrating SAS/STP control in a SATA storage device. Features and aspects hereof permit direct coupling of the SATA storage device to either a SATA host or to an STP initiator without requiring an intervening SAS expander.

Apparatus and methods for improved SATA device interaction without a SAS expander

A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Large transmissions on packetized data bus

An elasticity buffer has a reset input that, when activated, causes the elasticity buffer to temporarily cease operation. When the reset input bit is released, the elasticity buffer may resume operation. During periods when a device on a serial bus may be halted for power saving mode, for example, the serial communication may be reestablished and then the elasticity buffer may be released to continue operation.

Elasticity buffer restarting

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Active FIFO threshold adjustment

A high speed, two-way serial interface with a scrambler and de-scrambler may be tested by sending a single word repeatedly through the scrambler to create a pseudo-random sequence. The pseudo-random sequence is then passed through the transmitter and looped back through the receiver of the serial interface. The pseudo-random sequence is then descrambled and compared to the input word. Since the input sequence is only a single word rather than a series of words, the comparison is very simple and capable of being performed within the serial interface itself without the need for external test equipment.

High speed serial interface test

An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system

An apparatus generally comprising a plurality of writeable registers, a control circuit, and a transmitter circuit. The writeable registers may be configured to store (i) a first burst value and (ii) a first gap value. The control circuit may be configured to generate an idle signal (i) in a transmit state for a first duration determined by the first burst value and (ii) in an idle state for a second duration determined by the first gap value in response to a first command signal. The transmitter circuit may be configured to (i) enable transmitting while the idle signal is in the transmit state and (ii) disable transmitting while the idle signal is in the idle state.

Programmable transmission and reception of out of band signals for serial ATA

A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.

Programmable digital filter implementation for loss-of-signal detection for serial communications applications

A shift register is provided to monitor the difference between the read and write pulses to an elasticity buffer. The shift register essentially eliminates the need for any math functions in the elasticity buffer management logic. The shift register is as wide as the elasticity buffer is deep. In other words, for every word in the elasticity buffer, the shift register has a corresponding bit. Each time a word is written into the elasticity buffer without a simultaneous corresponding read, a value of '1' is shifted from a first end into the shift register, indicating that a space has been taken in the elasticity buffer. For every word read out of the elasticity buffer without a simultaneous corresponding write, a value of '0' (zero) is shifted from a second end of the shift register, indicating that one more space is available. The elasticity buffer management logic need only monitor the shift register value to determine whether the elasticity buffer is nearly empty or nearly full, and if fill words need to be inserted or deleted.

Shift register control of a circular elasticity buffer

A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.

Programmable polarity for high speed differential interfaces

An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bit (LSB) or from LSB to MSB. Therefore, when the first device is used with a second device, integrated circuit (IC) or logic, which can handle the serial data in only one order, the first device is programmed, or configured, to handle the serial data in the same order as the second device.

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Loveland, CO, United States of America

Steven Schauer