Intel Corporation

Steven S Poon

Timothy J Maloney

A reduced capacitance diode. A first conductive layer provides conductive interconnects for pad and supply diffusion regions in a diode. A second conductive layer includes a first portion to couple the pad diffusion regions to a pad and a second portion to couple the supply diffusion regions to a voltage supply. Lines of the first and second conductive layers are substantially parallel to each other in a diode region of the diode. Further, for one aspect, a tap for the diode to be coupled to a supply is wider than a minimum width.

Low-capacitance electrostatic discharge protection diodes

A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.

Multi-stack power supply clamp circuitry for electrostatic discharge protection

An electrostatic discharge protection circuit is provided having a first electrically conductive element (such as a current sinking transistor) to couple between a power source and a first node. The first electrically conductive element has a control input terminal. A discharge path control circuit having an output terminal couples to the control input terminal of the first electrically conductive element. A timer circuit having an output terminal couples to the input terminal of the discharge path control circuit. A ring oscillator timer circuit having an output terminal couples to an input terminal of the timer circuit. The ring oscillator timer circuit may include a series of inverter circuits and/or counter circuits (such as flip-flop circuits).

Electrostatic discharge protection circuit having a ring oscillator timer circuit

Apparatus and systems, as well as methods and articles, may operate to transmit an initial pulse to a directional coupler, where the initial pulse has an initial amplitude and a timed overshoot of a selected duration. Further activities may include stepping down the initial amplitude to an amplitude approximately equal to the initial amplitude times a mode reflection coefficient squared. A tuning stub may be coupled to a charge line to transmit the initial pulse, and decoupled from the charge line to refrain from receiving an echo pulse associated with the initial pulse.

Pulse transport apparatus, systems, and methods

A multi-stack power supply clamp circuit for providing electrostatic discharge (ESD) protection to enhance performance of advanced submicron processes is provided. The clamp circuit includes a bias voltage generator with low leakage and high current drive capabilities, and means to lighten current load on the voltage generator through reduced gate leakage. The bias voltage generator has includes a differential amplifier. The multi-stack clamp circuit provides voltage-tolerant ESD protection with optimized leakage, reduced sensitivity to operating conditions, and tolerance of increased gate current in new process technologies.

An electrostatic discharge circuit may include an RC timer that may be used to control the operation of two or more tiers within the ESD circuit.

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Santa Clara, CA, United States of America

Steven S Poon