Other

Synopsys, Inc.

Mentor Graphics Corporation

Steven S Greenberg

Joseph E Rodriguez

Du V Nguyen

An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.

Selectively reducing the number of cell evaluations in a hardware simulation

In the simulation of an analog and mixed-signal analog-digital physical circuit, events are assigned scheduled times. The events are stored in buckets in a hash table, with the scheduled times of the events in each bucket associated with the bucket. The scheduled times are organized into a heap, with the earliest scheduled time at the root of the heap. The earliest scheduled time is removed from the heap, and the events in the associated bucket are performed. Performing the scheduled events can cause new events to be scheduled, and existing events to be de-scheduled. When all the events in the bucket associated with the earliest scheduled time are simulated, the remaining scheduled times are re-organized into a new heap, and the steps of removing the earliest scheduled time, performing the scheduled events, and re-organizing the remaining scheduled times are repeated.

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Beaverton, OR, United States of America

Steven S Greenberg