Cadence Design Systems, Inc.

Steven Roberts Durrill

Taranjit Singh Kukal

Arnold Ginetti

Vikas Kohli

Amit Kumar Sharma

Utpal Bhattacharyya

Arnold Jean Marie Gustave Ginetti

Balvinder Singh

Nikhil Gupta

Vikrant Khanna

Madhur Sharma

Frank X Farmar

Tyler James Lockman

Ritabrata Bhattacharya

Abhay K Agarwal

Keith Felton

Abhishek Dabral

Chris Cheung

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic ('EM') model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

System and method to generate schematics from layout-fabrics with a common cross-fabric model

A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness

Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.

Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics

Various embodiments automatically back annotate an electronic design representation by inserting complex model instances in the representation and interconnecting the model instances with one or more interconnect models. Identifications of ports in a first representation may be associated or updated with identifications of corresponding ports in a second representation. Annotating the first representation may also include associating or stitching parasitic information from the second representation with or in the first representation. A model is used to represent a vectored net by splitting a vectored net with a vectored net identification into multiple scalared net segments each having its own scalared net identification. Some aspects automatically generate a display for visualizing results of annotating an electronic design with complex models. Some of these aspects may further include parasitic information and analysis results in the display.

Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs

A method of generating a representation of an electronic circuit across a plurality of design entry tools includes extracting a first partial circuit including a first plurality of first electronic components from a first partition, extracting a second partial circuit including a second plurality of second electronic components from a second partition, generating a simulation block in the first design entry tool including an interface between the first and second partitions, exporting a first netlist representing the interconnection of the first electronic components in the first partial circuit, populating the simulation block in the second design entry tool to include a second netlist representing the interconnection of the second electronic components in the second partial circuit and the interface between the first and second partitions, and exporting the second netlist to stitch the extracted first and second partial circuits using the interface between the first and second partitions.

Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulation

An interface object library tool for manipulating interface objects for a printed circuit board (PCB) tool is disclosed. The interface object library tool includes a hierarchical interface display module, an input module, and a store. The hierarchical interface display module is configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines. The plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects. The input module is configured to: accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments; and accept association between the plurality of interface objects and a plurality of groups. The store is configured to retain the plurality of interface objects; the plurality of groups; the plurality of signal, power and ground lines; and associations between these three.

Hierarchical editing of printed circuit board pin assignment

A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.

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Campbell, CA, United States of America

Steven Roberts Durrill