International Business Machines Corporation

Steven Robert Testa

Richard William Doing

James Norris Dieffenderfer

Brian Stempel

Kenichi Tsuchiya

John K Whetzel

Keith D Richeson

James L Carlisi

Thuong Quang Truong

John R Patty

Game board

A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.

Preventing livelocks in processor selection of load requests

A blade server assembly is disclosed that includes a blade server chassis, a blade server, and a support assembly connected with the blade server chassis and with the blade server so as to support the blade server substantially outside the blade server chassis. A method is also disclosed for maintaining a blade server installed in a blade server chassis that includes supporting the blade server substantially outside the blade server chassis through a support assembly connected with the blade server chassis and with the blade server.

Blade server assembly

A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

Apparatus and method for decreasing the latency between instruction cache and a pipeline processor

Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor

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Durham, NC, United States of America

Steven Robert Testa