Cadence Design Systems, Inc.

Steven Riley

Arnold Ginetti

Karun Sharma

Regis R Colwell

Jeffrey Markham

Chung-Do Yang

Joshua Alexander Baudhuin

Sabra Rossman

Gary Matsunami

Jose A Martinez

Khalid ElGalaind

Thomas Jordan

Embodiments according to the present disclosure relate to physically implementing an integrated circuit design while conforming to the requirements of complex color based track systems. In embodiments, the color based track systems can include irregularly spaced and non-uniform width colored tracks. These and other embodiments include a methodology to automatically generate a track pattern for an integrated circuit design that satisfies both design constraints and user inputs. Various alternatives for identifying starting points in the design for automatically generating track patterns are possible.

Generating a colored track pattern of non-uniform width from a sparse set of tracks

A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

Growing community of inventors

San Jose, CA, United States of America

Steven Riley