Arm Limited

Steven Richard Mellor

Paul Kimelman

Edmond John Simon Ashfield

Ian Field

Partha Prasun Maji

A bidirectional communications link between a master device and a slave device includes first endpoint circuitry coupled to the master device generating forward data packets, second endpoint circuitry coupled to the slave device for receiving reverse data packets, and bidirectional communication circuitry for transferring forward data packets from the first endpoint circuitry to the second endpoint circuitry and reverse data packets from the second endpoint circuitry to the first endpoint circuitry. In response to a power down condition requiring a power down of at least one of the first endpoint circuitry and the second endpoint circuitry, performance of said power down is deferred until both said outstanding forward credit signal and said outstanding reverse credit signal have been de-asserted.

Apparatus and method for providing a bidirectional communications link between a master device and a slave device

A system-on-chip integrated circuitincludes a packet transmitterfor generating data packets to be sent via a communication circuitto a packet receivercontaining a buffer circuit. A transmitter counterstores a transmitter count value counting data packets sent. A receiver counterstores a receiver count value tracking data packets emptied from the buffer circuit. A comparison circuitryis used to compare the transmitter count value and the receiver count value to determine whether or not there is storage space available within the buffer circuitto receive transmission of further data packets. The packet transmitteroperates in a transmitter clock domain that is asynchronous from a receiver clock domain in which the packet receiver operates. One of the count values is passed across this asynchronous clock boundary in order that the comparison may be performed and flow control exercised.

Data packet flow control across an asynchronous clock domain boundary

A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

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Sheffield, United Kingdom

Steven Richard Mellor