Globalfoundries Inc.

Globalfoundries U.S. Inc.

International Business Machines Corporation

Stmicroelectronics Gmbh

Globalfoundries Singapore Pte. Ltd.

Globalfoundries Dresden Module One Limited Liability Company & Co. Kg.

Globalfoundaries Inc.

Qcept Investments, LLC

Steven R Soss

Steven J Bentley

Ruilong Xie

Daniel Chanemougame

Julien Frougier

Mahbub Rashed

Suresh Venkatesan

Bipul C Paul

Subramani Kengeri

Marc Laurent Tarabbia

Irene Y Lin

Chinh Nguyen

Jeff Kim

Scott C Johnson

Hui Zang

Chanro Park

Ajey Poovannummoottil Jacob

Lars W Liebmann

Andreas Knorr

Akhilesh Ramlaut Jaiswal

Edward J Nowak

Eng Huat Toh

John H Zhang

Shyue Seng Tan

Min Gyu Sung

Siva P Adusumilli

Jongwook Kye

Xusheng Kevin Wu

Jiehui Shu

Shesh Mani Pandey

Haigou Huang

Murat Kerem Akarvardar

Yi Qi

Lindsey H Hall

Alban Zaka

Desmond Jia Jun Loy

Randolph F Knarr

Brett H Engel

Tom Herrmann

Nigel Graeme Cave

Yunfei Deng

M Brandon Steele

Jin Zheng Wallner

Yuansheng Ma

Rohit Galatage

David F Hilscher

Rod Augur

Seung-Hyun Rhee

Leitao Liu

Bum Ki Moon

James Benjamin Gullette

Scott Johnson

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

Semiconductor device with transistor local interconnects

The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.

Non-volatile transistor embedded static random access memory (SRAM) cell

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

Memory device and a method for forming the memory device

Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.

Charge-trapping sidewall spacer-type non-volatile memory device and method

A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.

Semiconductor device with metal structure under an active layer

A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.

Circuit structure and method for memory storage with memory cell and MRAM stack

Methods form devices by creating openings in sacrificial gates between nanosheet stacks (alternating layers of a first material and channel structures), forming spacers in the openings, and removing the sacrificial gates to leave the spacers. The first material is then removed from between the channel structures. A first work function metal is formed around and between the channel structures. Next, first stacks (of the stacks) are protected with a mask to leave second stacks (of the stacks) exposed. Then, the first work function metal is removed from the second stacks while the first stacks are protected by the mask and the spacers. Subsequently, a second work function metal is formed around and between the channel structures of the second stacks. A gate material is then formed over the first work function metal and the second work function metal.

Nanosheet field effect transistor with spacers between sheets

The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

Circuit structure and memory circuit with resistive memory elements, and related methods

One illustrative MRAM device disclosed herein includes a first bit cell and a second bit cell. The first bit cell comprises a first access transistor and a first MTJ stack. The first MTJ stack comprises a first pinned layer and a first free layer, wherein the first pinned layer is connected to the first access transistor. The second bit cell comprises a second access transistor and a second MTJ stack. The second MTJ stack comprises a second pinned layer and a second free layer, wherein the second free layer is connected to the second access transistor.

MRAM device comprising random access memory (RAM) and embedded read only memory (ROM)

A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

Vertical-transport field-effect transistors having gate contacts located over the active region

The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.

Method for forming replacement metal gate and related structures

The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

Product that includes a plurality of vertical transistors with a shared conductive gate plug

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Monroe, NY, United States of America

Steven R Soss