Intel Corporation

Arris Group, Inc.

Arris Enterprises LLC

Steven R Page

Robert C Duzett

Darin J Klaas

Sydney D Lovely

Yen-Cheng Liu

Bahaa Fahim

Jeffrey D Chamberlain

David B Johnson

Gunnar Gaubatz

Ronald J Ebersole

Joel C Huang

Antonio Juan

Krishnakumar Ganapathy

Manfred Neugebauer

Pau Cabre

Keith S Self

In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

Method, apparatus and system for modular on-die coherent interconnect for packetized communication

One or more I/O channels are assigned masks of message types that may pass through the channels, and one or more fields of an outbound message are set to one or more message type. A channel mask of an I/O channel is applied to a type of the outbound message, and if the channel mask matches the type of the outbound message, the outbound message is allowed to pass through the I/O channel to a switch. The outbound message is switched to an output port, and if the channel mask does not match the type of the outbound message, the outbound message is rejected from passing through the I/O channel and the channel mask of a next I/O channel is applied to the type of the outbound message.

Virtual networks in a communication system architecture

A media server comprises a plurality of nodes each comprising a gateway, each gateway providing memory and communication of data between mass storage and I/O ports of a node, and/or providing communication of data between the node and other nodes. Each node utilizes one or more central processors. The media server comprises logic to enable the processors to manage the streaming of data from the mass storage to the I/O ports via the gateways without communicating the data between the processors and any of the mass storage, I/O ports, or gateways.

Media stream distribution system

Control logic for controlling references to a cache (24) including a cache directory (62) which is capable of being configured into a plurality of ways, each way including tag and valid-bit storage for associatively searching the directory (62) for cache data-array addresses. A cache-configuration register and control logic (64) splits the cache directory (62) into two logical directories, one directory for controlling requests from a first processor and the other directory for controlling requests from a second processor. A prefetch buffer (63) is provided along with a prefetch control register for splitting the prefetch buffer into two logical channels, a first channel for handling prefetches associated with requests from the first processor, and a second channel for handling prefetches associated with requests from the second processor.

Bus expander with logic for virtualizing single cache control into dual

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Hillsboro, OR, United States of America

Steven R Page