Advanced Micro Devices Corporation

Steven R Klassen

Sanjiv K Lakhanpal

Atish Ghosh

Hans L Magnusson

Mark D Nicol

Chandrakant Pandya

Trent Johnson

John Heon Yi

Michael J Borsch

Satwant Singh

Jeff Brinkley

Glenn Eubank

Michael Gregory Tarin

A technique for observing signaling on the traces between ICs on a PC board without introducing significant signal degradation is provided. A route-through connector footprint allows the use of a standard connector without the use of stub traces. The route-through connector footprint allows a standard connector to be introduced directly into the line traces routed between ICs. Because stub traces are not used, this technique for mechanical interconnection into the line traces on a PC board allows for a single board layout to be used for both test and production. Additionally, because stub traces are not used, signal quality is minimally impacted and testing can be performed at operational speeds improving the reliability of the test function. The use of a route-through connector footprint additionally saves PC board space and cost.

Mid-bus connection to traces on a printed circuit board

A burn-in test system. A burn-in test system includes a device under test (DUT), a temperature controller coupled to the DUT, and a test controller. During testing, the test controller: (a) sets a parameter of the DUT to a first value and applies a test stimulus to the DUT, and (b) sets the parameter of the DUT to a second value and applies the test stimulus to the DUT. A change in the value of the parameter results in a change in the amount of heat dissipated by the DUT. The temperature controller maintains the DUT at a pre-determined temperature during testing with the parameter set to both the first and the second values. The DUT may be further coupled to a module that comprises circuitry employed in a product-level application environment. The module is configured by the test controller to simulate a product-level application.

Burn-in using system-level test hardware

A split-transaction bus decoder receives a plurality of packets, the plurality of packets including a request packet and a response packet, wherein the request packet includes an address and a request tag; and the response packet includes a command, a response tag, and data. Upon receipt of the request packet, the decoder stores the address and the request tag. Upon receipt of the response packet, the decoder matches the response tag to the request tag. The decoder produces a decoded packet including the address of the request packet and the command and the data of the response packet.

Split-transaction bus decoder

An improved split-transaction bus intelligent logic analysis tool has a bus synchronizer, a decoder and a logic analysis function. The bus synchronizer is configured to receive link traffic and frame the link traffic into a plurality of framed packets, the plurality of framed packets including a plurality of request packets and a plurality of response packets. The decoder is configured to receive the plurality of framed packets and decode the plurality of framed packets into decoded packets, wherein at least one of the decoded packets includes information from a request packet and information from a corresponding response packet. The logic analysis function is configured to receive the decoded packets and initiate a trigger action on receipt of one of the decoded packets.

Split-transaction bus intelligent logic analysis tool

An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections. Each section is associated with a given histogram time period.

Apparatus and method for monitoring the performance of a microprocessor

An apparatus and method are presented for monitoring the performance of a microprocessor. The apparatus includes performance monitoring hardware incorporated within the microprocessor. The performance monitoring hardware includes a memory unit for storing performance data. The memory unit includes multiple memory locations, each memory location being accessed by a unique set of address signals. Circuitry within the performance monitoring hardware produces the address signals. In one embodiment, the performance monitoring hardware includes an event select register array and circuitry for producing a set of high order (i.e., most significant) address signals. The event select register array preferably includes several event select registers for storing binary codes corresponding to selected events. A performance data acquisition period is divided into multiple histogram time periods of equal length. The high order address signals partition the memory unit into sections. Each section is associated with a given histogram time period and contains at least n memory locations, where n is the number of event select registers and the maximum number of selected events. Each section of the memory unit is used to store performance data relating to the selected events which occur during the corresponding histogram time period. Each occurrence of one of the n selected events during a given histogram time period results in the incrementing of the contents of a corresponding memory location within the corresponding section of the memory unit.

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Austin, TX, United States of America

Steven R Klassen