International Business Machines Corporation

Steven R Houghtalen

Raymond E Losinger

Joseph P Buonomo

James W Valashinas

Sivarama K Kodukula

Palmer W Agnew

Anne S Kellerman

Robert William Callahan

Harry L Tredennick

Brion N Shimamoto

A microprocessor chip which is capable of executing a specific subset of instructions on behalf of the main storage portion of a computer memory can be made to emulate direct execution instructions not in that specific subset while working on behalf a control storage portion of the computer memory in a manner which is transparent to the main storage portion by means of a novel set of operand space selection instructions in the control storage portion and a novel switching circuit on the microprocessor chip which controls the access of the chip to the control store portion and the main store portion.

Microprocessor implemented data processing system capable of emulating

The performance of a multimicroprocessor implemented data processing system that emulates a mainframe is enhanced by providing a pair of override latches that serve to steer accesses between main and control storage for instruction fetch and operand acquisition in a manner that minimizes the complexity and size of microprocessor interface microcoding. This is achieved by connecting the instruction and operand override latches between a primary microprocessor, a secondary microprocessor, off-chip control storage belonging to the secondary microprocessor, particularly memory mapped private storage therein, and main storage. The override latches are made responsive, via microcode provided for that purpose, to the type and cause of each memory access. The override latches are set or reset by a memory mapped write to a predefined address in the secondary control store after being enabled by control lines responsive to the particular microprocessor action being taken. When set, the instruction override latch directs all expected primary processor main storage instruction fetches to control store. When set, the operand override latch directs all expected primary processor main storage operand accesses to control store. As appropriate for instruction execution, either one or both of the primary or secondary microprocessors can thereby be transparently latched to main or control storage.

Storage selection override apparatus for a multimicroprocessor

Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. A mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off-chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip. The application of this method requires partitioning that makes each identified high performance subset executable on one microprocessor in the current state of technology, a way to quickly pass control back and forth between all of the microprocessors, a suitable way to pass data back and forth between all of the microprocessors, and a technology in which it is economically feasible to have several copies of a complex data flow and control store mechanism.

Methods for partitioning mainframe instruction sets to implement

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Endicott, NY, United States of America

Steven R Houghtalen