Micron Technology Incorporated

Intel Corporation

Steven R Eskildsen

Mostafa Naguib Abdulla

Suresh Rajgopal

Richard B Foehringer

David S Brannam

Robert Naylor Schenck

Jeffrey C Franz

Chan H Yoo

Yi Xu

Akshay N Singh

Dustin James Carter

Aravind Ramamoorthy

Liana Foster

Deborah S Kaller

Dan E Soto

Henrico L Yahja

Duane R Mills

John G Meyers

Suresh V Golwalkar

Jason Snodgress

Tito Barrios

Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

Apparatus having a multiplexer for passive input/output expansion

A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device. The decoder component is to decode the received signal and transmit the decoded signal to each of the set of memory devices. The decoded signal is to enable the transmission of the data between the multiplexer and the corresponding memory device via the particular output channel.

Selection component that is configured based on an architecture associated with memory devices

A selection device can be operatively coupled with non-volatile memory devices. Enable signals that are based on an architecture of non-volatile memory devices can be received. Data can be transmitted to the non-volatile memory devices based on the enable signals that are based on the architecture of the non-volatile memory devices.

Apparatus having first and second sets of memory devices commonly connected to receive a first enable signal and a second enable signal, respectively, and a multiplexer connected to receive the first and second enable signals. The multiplexer is configured to connect the first set of memory devices to an output of the apparatus in response to the first enable signal having a first logic level, and to isolate the first set of memory devices from the output in response to the first enable signal having a second logic level different than the first logic level. The multiplexer is further configured to connect the second set of memory devices to the output in response to the second enable signal having the first logic level, and to isolate the second set of memory devices from the output in response to the second enable signal having the second logic level.

Apparatus having multiplexers for passive input/output expansion and methods of their operation

A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

Face down dual sided chip scale memory package

Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of stacked memory dice, with at least some of the plurality of stacked memory dice include a Chip Enable (CE) signal connection electrically accessible from a surface of a corresponding one of the dice. Each of the stacked dice having the CE signal connection is controllable individually by a unique CE signal applied to the CE signal connection. Other apparatuses are disclosed.

Independent control of stacked electronic modules

Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.

Package including an interposer having at least one topological feature

Apparatus and methods are disclosed to allow independent control of stacked memory modules. In one embodiment, an apparatus may comprise first, second, and third modules, each of the first, second and third modules having a plurality of stacked memory dice, at least some of the plurality of stacked memory dice including a Chip Enable (CE) signal electrically accessible from a bottom surface of a corresponding module of the first, second and third modules. The apparatus may comprise a Package-on-Package (PoP) structure where the first, second and third modules are attached to one another such that an individual access to each CE signal associated with the PoP structure is provided from the bottom surface of the corresponding module.

Signal shifting to allow independent control of identical stacked memory modules

Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects.

Methods for receiving and transmitting voltage through the use of supply voltage or ground connections including bond pad interconnects for integrated circuit devices

Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.

Supply voltage or ground connections for integrated circuit device

Supply voltage or ground connections including bond pad interconnects for integrated circuit device

A memory device having die-stacking modules that are interchangeable within a Package-on-Package (PoP) and provide separate Chip Enable (CE) signals for all memory die in the die-stacking modules.

Growing community of inventors

Folsom, CA, United States of America

Steven R Eskildsen