Siemens Information & Communication Networks, Inc.

Siemens Communications, Inc.

Symmetricom, Inc.

Steven R Cole

Abid Farooq

Russell T Baca

Samer H Darras

Marcel Manzado

A packet probe for a packet network accurately generates and monitors packets within the network. The packet probe supports packet generation and packet transmission. When a packet is ready for transmission, a hardware-based time stamp unit affixes a time stamp to the packet reflecting an actual transmission time. The packet probe also supports receiving, filtering, and time stamping received packets. When a packet is received, a packet filter determines whether the received packet should be stored in memory along with a time stamp reflecting an actual reception time.

Method and apparatus for monitoring packet networks

A system, method, apparatus, means, and computer program code that facilitate conversion of a single data stream into two or more data streams (e.g., a down rate conversion) and for systems, means and that facilitate conversion of two or more input data streams into a single output data stream (e.g., an up rate conversion). According to some embodiments of the present invention, for an up rate conversion of two or more input data streams into a single output data stream, bits from the input data stream are shifted through a set of shift register elements or other storage positions on each clock cycle, but bits are only loaded into shift register elements on every other clock cycle. In contrast, according to some embodiments of the present invention, for a down rate conversion of a single input data stream into two or more separate output data streams, bits from the input data stream are loaded into pairs of shift register elements or other storage positions on each clock cycle, but are shifted through the shift register elements only on every other clock cycle.

Methods and apparatus for conversion of one or more data streams

A system and method for filtering a jittered clock is disclosed. The filter of the present invention may check if a reference clock is received at a point in time within a pre-defined window of time. If the clock is received at a point in time within the window, the reference clock may be utilized as a reference for a system application such as a reference for a phase-locked loop. If the reference clock is not received at a point in time within the window, an interpolated clock representing an ideal received clock may be utilized. This may minimize the disturbance of system applications by blocking extreme deviations of the reference clock.

Digital interpolation window filter for phase-locked loop operation with randomly jittered reference clock

A telecommunications system ( ) is provided that includes a first controller ( ) and a second controller ( ) coupled using a packet-switched network ( ). The controllers provide a low cost means of coupling isochronous telecommunication devices. The first controller ( ) receives one or more isochronous input channels from a common control shelf ( ), such as a private branch exchange (PBX), over a circuit-switched network ( ). The first controller ( ) encapsulates an isochronous frames from the common control shelf ( ) into a data frame that is transferrable over the packet-switched network ( ). The second controller ( ) is configured to receive the data frame and extract the isochronous frame, which is then transmitted to a peripheral shelf ( ), such as a line trunk unit (LTU), using an isochronous circuit-switched network ( ). The controllers contain identical functionality, permitting bi-directional transmission of data between the common control and peripheral shelves. Each controller includes multiplex/de-multiplex functions normally associated with isochronous telephony, as well as a packetize/de-packetize functions for transferring data over the packet-switched network ( ). The arrival rate of the data packets is used for synchronizing the two controllers.

Apparatus and method for interconnecting isochronous systems over packet-switched networks

A method of automatically selecting a mode of operation during an initialization sequence of a multi-mode signal controller includes selectively enabling and disabling signal reception and signal driving capabilities and includes monitoring the remaining signal traffic to determine the position of the controller along a communication path. In the preferred embodiment, the signal controller is one of at least two identical signal controllers along a single communication path. For example, the controllers may be components at opposite sides of a telecommunications link of a PBX or other telecommunication system. The structurally identical controllers perform mirror image operations when the controllers are properly initialized to restrict the controllers to different modes of operation. In the initialization sequence for a particular signal controller, the signal reception is monitored to determine whether the controller is receiving a known pattern of system control, such as a universally applied clock signal. Detection of the system control signal clearly identifies the controller as being on the same side of the telecommunications link as the source of the system control signals. On the other hand, the telecommunications link may be monitored for communication signals from the other signal controller. Detection of the communication signals identifies the initializing controller as being on the opposite side of the telecommunications link from the source of the system control signals.

Device and method for automatic initialization of a multi-mode interface controller

A synchronization circuit (,) includes three flip-flops responsive to a common clock signal (CLK,). The input to the first flip-flop (,) represents the least significant bit (LSB) of a counter (,) included within a first clock domain. The CLK,signal originates from a second clock domain. The output of the first flip-flop is provided as input to the second flip-flop (,), and the second flip-flop output is provided as input to the third flip-flop (,). An exclusive-or (XOR) gate (,) generates a synchronization signal in response to outputs of the second and third flip-flops (,). The synchronization signal is usable within the second clock domain and activate for one period of CLK,subsequent to every transition occurring on the LSB input. The active state of the synchronization signal indicates that a predefined set of data inputs is stable and valid. In this manner, a single unsynchronized input signal, i.e., the LSB input, can be used to synchronize the data inputs.

Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains

A method and system of enabling intra-system communication between first and second microprocessors in an asynchronous transfer mode (ATM) environment includes emulating ATM segmentation and reassembly at the first microprocessor. The second microprocessor is connected to circuitry for supporting ATM communications with other systems. With respect to an inter-processor communication (IPC) from the first microprocessor to the second microprocessor, conventional ATM segmentation is emulated at the first microprocessor, thereby forming fixed-length cells having payloads representative of the IPC. ATM-compatible header information is attached to each one of the cells and transferred to the circuitry, which typically includes a segmentation and reassembly (SAR) device. The circuitry reassembles the message and forwards the IPC to the second microprocessor. With respect to an IPC directed from the second microprocessor to the first microprocessor, the message is segmented at the circuitry to form fixed-length cells having payloads representative of the message. ATM-compatible header information identifying the first microprocessor as the destination is attached to each of the cells. The cells are then transferred to the first microprocessor, where conventional ATM reassembly of the message is emulated.

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San Jose, CA, United States of America

Steven R Cole