International Business Machines Corporation

Steven R Carlough

Brian Robert Prasky

Fadi Y Busaba

Christopher A Krygowski

Eric M Schwarz

Chung-Lung K Shum

Silvia Melitta Mueller

Gary A Van Huben

Susan M Eickhoff

Patrick James Meaney

Jonathan D Bradbury

Stephen J Powell

Petra Leber

Jie Zheng

Reid T Copeland

Wen H Li

Timothy John Slegel

Adam B Collura

Klaus Michael Kroener

Charles W Gainey, Jr

Marcel Mitran

John G Rell, Jr

Juergen Haess

Michael Klaus Kroener

Kerstin Claudia Schelm

Michael Klein

Sheryll H Veneracion

Cedric Lichtenau

Phillip G Williams

Daniel Lipetz

Michael B Spear

Erez Barak

Son Trong Dao

Eyal Gonen

Warren Edward Maule

Kurt Alan Feiste

David S Hutton

Stephen Dale Wyatt

Andreas Wagner

William John Starke

Jeffrey A Stuecheli

Brian William Thompto

Gregory William Alexander

Lee Evan Eisen

Wilhelm Ernst Haller

David Andrew Schroter

James Raymond Cuffney

Christophe J Layer

Mark Alan Erle

Markus Cebulla

Paul M Kennedy

Logan I Friedman

Walter Pietschmann

Nicholas Steven Rolfe

Paulomi Kadakia

Mark S Farrell

Charles Franklin Webb

Bruce Martin Fleischer

Craig Raymond Walters

Albert James Van Norstrand, Jr

Mark Anthony Check

James Wilson Bishop

Nathan J Lee

Michael Wayne Harper

Joshua M Weinberg

Marcy Evelyn Byers

Manuela Niekisch

Michael R Kelly

Amy S Purdy

Adrian O Robinson

Chung-Iung K Shum

Frank Tanzi

Scott M Blackledge

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

A system and associated processes may perform a memory access operation that includes receiving a data packet comprising a command of a type of a plurality of types of commands. The processes may include initiating a decoding of a first portion of the command, and automatically speculating as to the type of the command. Based on the speculation as to the type of the command, a bank activate command may be generated before the data packet is entirely decoded or received.

Speculative bank activate dynamic random access memory (DRAM) scheduler

A calibration controller determines a latest arriving data strobe from at least one data chip at a first data buffer in a read data path between at least one memory chip and a host on a high speed interface. The calibration controller determines whether external feedback of the at least one data chip is required. The calibration controller, in response to determining that external feedback of the at least one data chip is required, aligns a chip clock distributed to a second data buffer in the read data path with the latest arriving data strobe by applying a 180 degree phase align of the chip clock through one or more latches, wherein data cross a first clock boundary from the first data buffer to the second data buffer, to minimize a latency in the read data path across the first clock boundary.

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Aspects of the invention include using a cyclic redundancy code (CRC) multiple-input signature register (MISR) for early warning and fail detection. Received bits are monitored at a receiver for transmission errors. The monitoring includes receiving frames of bits that are a subset of frames of bits used by the transmitter to generate a multi-frame CRC. At least one of the received frames of bits includes payload bits and a source single check bit not included in the multi-frame CRC. It is determined whether a transmission error has occurred in the received frames of bits. The determining includes generating a calculated single check bit based at least in part on bits in the received frames of bits, and comparing the received source single check bit to the calculated single check bit. An error indication is transmitted to the transmitter if they don't match.

Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection

In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.

Residue prediction of packed data

A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Reducing chip latency at a clock boundary by reference clock phase adjustment

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

Host controlled data chip address sequencing for a distributed memory buffer system

An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.

Interface scheduler for a distributed memory system

Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

Convert to zoned format from decimal floating point format

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Poughkeepsie, NY, United States of America

Steven R Carlough