Intel Corporation

International Business Machines Corporation

Steven R Carbonari

Tsung-Yuan Charles Tai

Patrick L Connor

Alexander W Min

Brian J Skerry

Ira Weiny

Jr-Shian Tsai

Iosif Gasparakis

Tom Long Nguyen

Thomas M Slaight

Nrupal R Jani

Wayne Alan Downer

Daniel J Dahle

Richard Lindsley

Examples may include techniques to enable synchronized execution of a command by nodes in a network fabric. A node capable of hosting a fabric manager for the network fabric (fabric manager node) may generate one or more packets including a command to be executed by at least some nodes in the network fabric. In some examples, a time stamp is also included with at least one of the one or more packets to indicate to receiving nodes to execute the command at a synchronized time.

Techniques for synchronized execution of a command at network fabric nodes

Technologies to monitor and manage platform, device, processor and power characteristics throughout a system utilizing a remote entity such as controller node. By remotely monitoring and managing system operation and performance over time, future system performance requirements may be anticipated, allowing system parameters to be adjusted proactively in a more coordinated way. The controller node may monitor, control and predict traffic flows in the system and provide performance modification instructions to any of the computer nodes and a network switch to better optimize performance. The target systems collaborate with the controller node by respectively monitoring internal resources, such as resource availability and performance requirements to provide necessary resources for optimizing operating parameters of the system. The controller node may collect local system information for one or all of the computer nodes to dynamically steer traffic to a specific set of computers for processing to meet desired performance and power requirements.

Technologies for directed power and performance management

In some embodiments, a method, apparatus and system for memory instructions in processors with embedded memory controllers are presented. In this regard, a memory agent is introduced to configure memory coupled with a processor through a memory interface by invoking one or more processor instructions dedicated to configuring memory. Other embodiments are also disclosed and claimed.

Method, apparatus and system for memory instructions in processors with embedded memory controllers

In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by copying contents of the address field and data field of an entry in the MRT into the address field and data field of the MSI. Other embodiments are described and claimed.

Message signaled interrupt redirection table

Computer-based devices, whether initiators or targets, are assured access to a bus having a fixed priority arbitration scheme (such as a SCSI bus) by assigning to each initiator a &ldquo;fair share&rdquo; of the bus bandwidth. This share is defined as a number of bytes per a unit of time such as a time period. The shares together total a fraction of the total bus bandwidth, with a margin of bus bandwidth left unassigned. To prevent initiator starvation, each initiator monitors its bus requests to determine if it is being prevented by higher-priority initiators from using its assigned share of the bandwidth. If not, the initiator periodically pings each higher-priority initiator to indicate that it is not being starved. So long as a higher-priority initiator continues to receive pings from all lower-priority initiators, the higher-priority initiator can continue to use as much bandwidth as it needs. If the higher-priority initiator fails to receive a ping from a lower-priority initiator, it stops sending new bus requests to the SCSI bus, making the bandwidth available to the lower-priority initiator. To prevent target starvation, each initiator monitors its outstanding bus requests to targets. If a request does not complete in an appropriate time, the initiator pings all other initiators with notification of target starvation. In response, all initiators limit their new bus requests to their share of the bandwidth. This limiting makes the unassigned margin of bus bandwidth available to the targets.

Method for assuring device access to a bus having a fixed priority arbitration scheme

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Beaverton, OR, United States of America

Steven R Carbonari