Intersil Americas Inc.

Megatest Corporation

Nextest Systems Corporation

Steven R Bristow

Patrick Sullivan

Jeffrey Allen King

William Robert Creek

Paul D Magliocco

Seth W Craighead

Paul Magliocco

A tester includes a device under test (DUT) power supply (DPS) with and input and output includes an amplifier configured to set an output voltage of the DPS output equal to an input voltage for the DPS. The DPS has a first output stage coupled to the amplifier and configured to source and sink current at the output of the DPS between a first voltage rail and a third voltage rail. The DPS has a second output stage coupled to the amplifier and configured to source and sink current to the output of the DPS between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Tester having device under test power supply

A power supply with and input and output includes an amplifier configured to set an output voltage of the power supply output equal to a fixed input voltage for the power supply. The power supply has a first output stage coupled to the amplifier and configured to source and sink current at the output of the power supply between a first voltage rail and a third voltage rail. The power supply has a second output stage coupled to the amplifier and configured to source and sink current to the output of the power supply between a second voltage rail and the third voltage rail. A selection device is configured to enable the first and second output stages based on a selection input signal. The selection device is situated outside of the first and the second output stages.

Device under test power supply

A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus ( ) includes: (i) pin electronics (P/Es ) each coupling the apparatus to one of a number of pins ( ) on device ( ); (ii) timing and format circuits (T/Fs ) for mapping a signal to one of P/Es ( ); (iii) pattern generator ( ) having a number of outputs for outputting signals for testing device ( ); (iv) pin scrambling circuit ( ) between pattern generator ( ) and T/Fs ( ), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock ( ) for providing a clock signal having a clock cycle to pattern generator ( ) and T/Fs ( ). T/Fs ( ) are capable of switching the signals coupled to P/Es ( ) at least twice each clock cycle.

Semiconductor test system having double data rate pin scrambling

A unique timing system is provided which allows for a user to program timing events with variable periods and edges from a fixed frequency clock, and having resolution greater than that of the fixed reference frequency. Delay elements, which are inherently expensive, inaccurate, and require repeated calibration, are minimized.

Growing community of inventors

San Jose, CA, United States of America

Steven R Bristow