Sun Microsystems, Inc.

Intergraph Corporation

Oracle America, Inc.

Zilog, Inc.

Steven R Boyle

Claude R Gauthier

Robert J Proebsting

Spencer Montgomery Gold

Bidyut Kanti Sen

Deviprasad Malladi

William H Herndon

Sergiu Radu

Shahid S Ansari

Hanxi Chen

Brian W Amick

Raymond A Heald

Kamran Zarrineh

Anand Dixit

Joseph Raymond Siegel

Kenneth Alan House

David Hockanson

Niraj Kumar

John E Will

A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

Method for monitoring and adjusting circuit performance

A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

Method and system for monitoring and profiling an integrated circuit die temperature

An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a circuit board.

EMI heatspreader/lid for integrated circuit packages

An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.

Integrated temperature sensor

An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI containment configuration. The second EMI containment configuration is disposed around the first EMI containment configuration. The first and second EMI containment configurations include vias coupled to at least one ground plane of the integrated circuit package.

Integrated circuit package with EMI containment features

A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient device debug system

A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient debug package design

A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias are placed near conductive vias to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals (e.g. CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

Method of making a multi-layer to package

Multi-layered integrated circuit package with improved high frequency

A technique is disclosed for manufacturing an integrated circuit die which is capable of being packaged in any of two or more different package types having different arrangements of bonding posts. The circuit is laid out with redundant pads located at different places on the die so that one pad in each pair of redundant pads is accessible for bonding with posts in one package type, while the other pad in each pair of redundant pads is accessible for bonding with posts in another package type. Illustrative layouts are shown whereby various types of pads, e.g., power pads, signal input pads, signal output pads and bidirectional I/O pads, may be made redundant.

Growing community of inventors

Santa Clara, CA, United States of America

Steven R Boyle