Motorola Corporation

Steven Peter Allen

William Chunhung Yip

Walter C Seelbach

Ahmad H Atriss

James Brian Piket

Gerald V Piosenka

William Robert Worger

Robert C Ledzius

Roman Casimir Lopatynski

Thomas R Troksa

Gerald Lee Walcott

Scott T Demarest

Robert J Durette

Robert C Ledszius

A voltage boosting circuit which derives an output voltage than is substantially twice the magnitude of a supply voltage applied thereto. The voltage boosting circuit consists of complementary acting boost circuits each having a pair of switches (42A, 52A; 42B, 52B) connected between an input of the voltage boosting circuit, at which is applied the supply voltage, and an output at which the output voltage is produced. Boost capacitors (48A, 48B) are connected between the respective switches of the complementary boost circuits and the switches of the these circuits are opened and closed out of phase with respect to each other in response to clocking signals being applied thereto such that a boosted output voltage is produced during each half cycle of the clocking signals.

Complimentary double pumping voltage boost converter

A technique and method that efficiently and simultaneously transfers both voice and data information over a single communications link (11). The technique and method utilizes a multi-rate vocoder (12) for providing voice information at a plurality of different rates. Accordingly, the vocoder may be dynamically adjusted during transfer of information to meet channel bandwidth requirements. The technique and method also utilizes a bit-control protocol for inserting voice information within a stream of data information by the use of inserting flags having predetermined bitstreams. Accordingly, voice information is dynamically inserted into an existing bitstream of data information such that voice information is transferred only upon demand and when needed. This prevents the transfer of useless information, such as voice information when a speaker is silent and, thus, allows for very efficient utilization of system bandwidth.

Simultaneous transfer of voice and data information using multi-rate

A quadrant detector circuit (400) has a comparator (442) having a pair of inputs (438, 440). A first (438) of the pair of inputs (438, 440) is coupled to an in-phase signal (434) and a second (440) of the pair of inputs (438, 440) is coupled to a quadrature phase signal (436). A sample counter (448) has a reset (446) coupled to an output (444) of the comparator (442). A controllable switch (456) has a selection input (454) coupled to an output (452) of the sample counter (448). The controllable switch (456) is capable of switching between a local oscillator signal (458) and an inverse local oscillator signal (460).

Balance differential receiver

Working assets (26) are equipped with ID tags (56) that respond to interrogations from interrogators (50). Each interrogated tag (56) sends response codes that identify the tag (56) and working asset (26), can describe an amount of use experienced by the working asset (26), and can describe unused capacity available for holding a consumable commodity, such as fuel. Interrogators (50) are positioned at normally closed portals (40, 42, 62, 64) of staging areas (22, 24). A database (94) contains information concerning working assets (26), users (28) to whom working assets (26) have been assigned, and caretakers (38) who may be authorized to transport various working assets (26). The caretakers (38) also have ID tags (58). A portal (40, 42, 62, 64) temporarily opens or remains closed in response to the interrogation that takes place at the portal (40, 42, 62, 64) and data stored in the database (94).

Working asset management system and method

A method and corresponding apparatus (10) for generating a pseudo-random number. The method has steps of generating a first bit stream from a number generator (16, 35), combining a predetermined number with the first bit stream to provide a second bit stream and feeding the second bit stream into a feedback port (32) of the number generator (16, 35).

Divergent code generator and method

An electronic tag (10) receives a data message (18) that has a wake-up section (20) followed by a session section (22). The interrogation signal which carries the data message encodes the wake-up section (20) differently from the session section (22). A power manager (28) decodes the wake-up section (20) using a very low power decoder (34) that remains energized during a standby state. When the power manager (28) detects a predetermined identification code (26), it controls a switching circuit (32) to energize a controller (30). The controller (30) may then decode, process, and respond to information conveyed during the session section (22). If the power manager (28) does not detect the identification code (26), the controller (30) remains de-energized. The power manager (28) also includes a synchronizer (38) which determines when a preamble (24) is detected, and an ID decoder (40) that determines when the wake-up section (20) conveys the predetermined identification code (26).

Low power addressable data communication device and method

A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.

Edge sensitive level translating and rereferencing CMOS circuitry

An integrated circuit which contains an on-chip clock that operates the integrated circuit at its true maximum speed is disclosed. The integrated circuit operates asynchronously from a processor bus and contains circuitry for interfacing with the processor bus. A clock generator is constructed using information obtained from identifying a slowest signal path of the integrated circuit. The clock may be stopped and started under processor control to permit communication between the IC and processor bus.

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Mesa, AZ, United States of America

Steven Peter Allen