Siemens Aktiengesellschaft

Siemens Industry, Inc.

Texas Instruments Corporation

Siemens Energy & Automation, Inc.

Steven Perry Parfitt

Steven Michael Hausman

William Keith Bryant

Steven M Hausman

Jeffrey Howe

Thomas Brian Hartley

A Functional Safety Counter Module is provided and it comprises input circuitry, test circuitry, a first microcontroller including a first hardware counter, a second hardware counter, a first storage device that stores a first firmware algorithm code to execute a counter pattern test in order to detect a short open input signal and/or a failure in counting capability of the first microcontroller and a second microcontroller including a third hardware counter, a fourth hardware counter, a second storage device that stores a second firmware algorithm code. The first and second firmware algorithm codes are configured to resynchronize and restore respectively a first counter or a second counter after the counter pattern test and are configured to detect an offset and adjust during a resynchronization process to account for the offset such that to successfully resynchronize two separate resynchronization algorithm codes are used depending on an input frequency of counter signals input to four hardware counters.

Functional safety high-speed counter module including diagnostics circuitry for performing counter pattern test

A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.

Fail-safe counter evaluator to insure proper counting by a counter

Certain exemplary embodiments can provide a system, which can comprise a signal interface that is adapted to transmit a signal between a programmable logic controller and an Input/Output (I/O) module. The programmable logic controller can be communicatively coupled to the I/O module via an opto-coupler, which can be adapted to electrically isolate the programmable logic controller from the I/O module.

Devices, systems, and methods regarding programmable logic controller communications

Certain exemplary embodiments can provide a method, which can comprise transmitting a recovered analog input signal to a programmable logic controller. The recovered analog input signal can be converted, on a downstream side of an isolation device, from a converted signal. The recovered analog input signal can have a voltage value that varies according to a frequency value of the converted signal.

Systems and/or devices for providing an isolated analog output or analog input

Certain exemplary embodiments can provide a system, which can comprise a circuit adapted to cause an actuation of an output device according to a control output. The control output can be generated comprising a control signal, the control signal extracted from a sequence of clock pulses. The sequence of clock pulses can comprise the control signal.

Devices, systems, and methods for reducing signals

At least one exemplary embodiment of the present invention includes a device that comprises a microprocessor, a multiplexing analog-to-digital converter integral to said microprocessor, and a reference voltage source connected to said multiplexing analog-to-digital converter. At least one exemplary embodiment of the present invention includes a method that comprises obtaining a signal at a multiplexing analog-to-digital converter integral to a microprocessor; and comparing a digital value of the signal to a reference digital value. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. This abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Analog to digital converter threshold detection circuit

A circuit for converting analog to digital data uses a CMOS multiplexer, an analog to digital converter and an operational amplifier buffer controlled by a single chip microprocessor. An FET shunt circuit is connected to the input of the operational amplifier in order to pull the input to ground during a conversion cycle of the converter and the resulting data is read and used to adjust the data from subsequent data conversions to correct for offsets of the operational amplifier and the converter.

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Johnson City, TN, United States of America

Steven Perry Parfitt