International Business Machines Corporation

Globalfoundries Inc.

Steven Paul VanderWiel

Charles Luther Johnson

Gerald Keith Bartley

Russell Dean Hoover

Michael Steven Siegel

Robert K Montoye

Jeffrey Haskell Derby

Timothy Hume Heil

Patrick Ronald Varekamp

Jeffrey Richard Summers

Dheeraj Sreedhar

Lixin Zhang

Jian Li

Charles D Johnson

Aaron Christoph Sawdey

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

High-performance hash joins using memory with extensive internal parallelism

An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Universal inter-layer interconnect for multi-layer semiconductor stacks

A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Hybrid bonding techniques for multi-layer semiconductor stacks

A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

Thermal enhancement for multi-layer semiconductor stacks

Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.

On-chip networks for flexible three-dimensional chip integration

A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack.

A design structure is provided for a slotted ring network, in which a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Structure for preventing starvation in a slotted ring data communications network

In a slotted ring network, a node may transmit a non-renewable slot reservation with any unreserved slot. The reservation restricts other nodes from transmitting a new packet in the slot. When the slot returns around the ring to the reserving node, the slot will be available. Preferably, reservation is made responsive to a starvation condition in the reserving node, which may be detected in any of various ways. In an optional enhancement, a reservation identifies the reserving node, and another node on the ring is free to transmit a new packet in the reserved slot if the new packet will reach its destination at or before the reserving node, and thus will not interfere with the reservation.

Method and apparatus for preventing starvation in a slotted ring data communications network

Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.

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Rosemount, MN, United States of America

Steven Paul VanderWiel