International Business Machines Corporation

Steven Paul Hartman

Eric Ernest Millham

Scott Whitney Gould

Christine Marie Fuller

Joseph Andrew Iadanza

Frank Ray Keyser, Iii

Kim P Clinton

Van Hoa Lee

Terrance John Zittritsch

Brian A Worth

Allan Robert Bertolet

Timothy Shawn Reny

Gulson Yasar

Michael Stephen Floyd

Malcolm Scott Ware

Robert H Bell, Jr

Michael Jay Shapiro

Louis Bennie Capps, Jr

Venkat Rajeev Indukuru

Mark Elliott Hack

Soraya Ghiasi

Rajendra D Panda

Joseph H Robichaux

Rick A Hamilton, Ii

Karthick Rajamani

Freeman Leigh Rawson, Iii

Scott Harlan Isensee

Juan C Rubio

Alongkorn Kitamorn

Thomas W Keller, Jr

Donald R DeSota

Andreas Bieswanger

Norman Karl James

Joel Gerard Goodwin

Hye-Young McCreary

Milton Devon Miller, Ii

Joshua D Friedrich

Gulsun Yasar

Harold Wayne Chase

Richard L Willaman

Wally Tuten

Donald R Desota

Ira Biggs

Joshua David Friedrich

Angle-adjustable connectors and modular systems capable of securing angle-adjustable side rails to trailers and/or trucks are described. The angle-adjustable connectors comprise a first component capable of attaching to a universal bracket of a trailer and a second component capable of securing one or more rail at a position disposed at a desired angle relative to the first component and/or a bed of the trailer or truck.

Angle-adjustable connector

According to one aspect of the present disclosure a method and technique for managing memory access is disclosed. The method includes setting a memory databus utilization threshold for each of a plurality of processors of a data processing system to maintain memory databus utilization of the data processing system at or below a system threshold. The method also includes monitoring memory databus utilization for the plurality of processors and, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocating at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.

Reallocating unused memory databus utilization to another processor when utilization is below a threshold

According to one aspect of the present disclosure a system and computer program product for managing memory access is disclosed. The system includes a plurality of memory controllers each configured to maintain memory databus utilization by a corresponding processor at or below a threshold to maintain memory databus utilization of the system at or below a system threshold. The system also includes a service processor configured to receive memory databus utilization data from the memory controllers and programmed to, in response to determining that memory databus utilization for at least one of the processors is below its threshold, reallocate at least a portion of unused databus utilization from the at least one processor to at least one of the other processors.

Memory databus utilization management system and computer program product

A benchmark tester retrieves a voltage margin that corresponds to a device that a system includes. The voltage margin indicates an additional amount of voltage to apply to a nominal voltage that, when added, results in the device operating at a power limit while executing a worst-case power workload. Next, the benchmark tester (or thermal power management device) sets an input voltage for the device to a value equal to the sum of the voltage margin and the nominal voltage. The benchmark tester then dynamically benchmark tests the system, which includes adjusting the device's frequency and input voltage while ensuring that the device does not exceed the device's power limit. In turn, the benchmark tester records a guaranteed minimum performance boost for the system based upon a result of the benchmark testing.

Identifying deterministic performance boost capability of a computer system

A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

Integrated circuit environment initialization according to information stored within the integrated circuit

A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

Unified management of power, performance, and thermals in computer systems

A method, computer program product, and a data processing system for maintaining operation of the data processing system in the event of a degraded system cooling condition is provided. A first temperature of a processor is identified as equaling or exceeding a processor throttling threshold. The operational frequency of the processor is reduced by a first frequency increment. The operational voltage of the processor is then reduced by a first voltage increment. Updated values of the processor temperature are periodically obtained and continued reductions in the frequency and operational voltage are made until the temperature indicates that the processor is operating in a stable throttle range. The frequency and operational voltage of the processor may be returned to normal levels when an updated temperature of the processor is less or equal to a throttle off threshold.

System and method to maintain data processing system operation in degraded system cooling condition

Method initializing an environment of an integrated circuit according to information stored within the integrated circuit

An apparatus and method for expansion of an inter-IC (I C) is provided. An expansion processor resides on a primary I C bus. The expansion processor is coupled to a plurality of I C sub-buses each of which may host a plurality of I C devices. Data is transferred between the expansion processor and the plurality of I C devices via the corresponding sub-bus according to an I C protocol. Data transfer is in response to a request initiated by a bus master on the primary I C bus. The bus master communicates with a target device residing on one of the sub-buses by addressing the expansion processor. The bus master informs the expansion processor of the target device by sending the expansion processor a number of the sub-bus on which the target device resides, and an address of the target device. A data stream bound for the target device is directed to the expansion processor which the echos it to the target device. Likewise, a data stream bound from the target device to the bus master on the primary I C bus is transmitted to the expansion processor which the echos it to the bus master.

12C bus expansion apparatus and method therefor

A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.

Burst instruction alignment method apparatus and method therefor

One aspect of the invention relates to an apparatus for detecting environmental faults in a computer system. In one version of the invention, the apparatus includes a means for measuring a physical parameter with a sensor coupled to the computer system, the sensor being associated with a sensor type and identification code; a means for transmitting a signal from the sensor to the computer system, the signal being responsive to the measurement; a means for determining whether an environmental fault condition exists by comparing the signal to a pre-determined threshold; means for determining an error type, identification code and sensor type; and a means for writing fault data to an environmental warning register, the fault data comprising the sensor type, identification code and error type.

Environmental and power error handling extension and analysis

A programmable logic cell has four cell input nodes and a plurality of combinational logic circuits. Four inverter circuits are provided for programmably inverting respective input logic signals, each inverter circuit having an inverter input node connected to a respective cell input node for accepting its respective input logic signal therefrom. Each inverter is programmable into a first state wherein a logic signal representing the complement of the input logic signal is provided to the inverter output node, and a second state wherein a logic signal representing the non-complement of the input logic signal is provided to the inverter output node. The inverter circuits buffer their input logic signals in both their first and second states. A first logic gate of the plurality of combinational logic circuits has first and second inputs each connected to a respective output node of one of two of the four inverter circuits, and a second logic gate has first and second inputs each connected to a respective output node of one of the other two of the four inverter circuits. The inverter circuits may be implemented as XNOR gates.

Programmable inverter circuit used in a programmable logic cell

In a Field Programmable Gate Array ('FPGA') design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.

Method and system for optimizing a critical path in a field programmable

A computer implemented method for the automated placement and routing in the design of field programmable gate arrays achieves optimal timing. In a library of primitives and macros from which a designer may choose to implement a given circuit design, at least some of said macros are 'semi-hard' macros where direct connections and relative placements are specified while local bus routing is requested in a manner that does not restrict macro placement. A logical netlist containing references to macros and how to connect them together to perform a logical function is first created. The logical netlist is then translated to a physical netlist using a mapper function. This physical netlist for the semi-hard macros specifies what is to be connected but not how. The best place to put each macro on the field programmable gate array is found using a placer function. The placer function thus determines an absolute position of the macros. Pre-defined macro direct connections are routed using a router function. The router function determines an optimal path to connect the semi-hard macros. Finally, a bitstream is generated from placement and routing information developed by the placer and router functions to program the field programmable gate array to perform the netlist logical function.

Field programmable gate arrays using semi-hard multicell macros

Growing community of inventors

Round Rock, TX, United States of America

Steven Paul Hartman