Harris Corporation

Xandex, Inc.

Fortinet, Inc.

Cosine Communications, Inc.

Steven Patrick Weir

Abraham Rabindranath Matthews

An output ripple voltage average amplitude of a switch mode DC-DC converter is dynamically maintained. The converter has a switch and an output filter. By varying a switching period (T) of the switch, Vis maintained at a substantially constant value over a first range of converter input voltages and a second range of switch duty cycles. Where the output filter includes an inductor having inductance (L) and a capacitor having capacitance (C) the average amplitude of Vis dynamically maintained by varying Twith respect to switch duty cycle (D) and input voltage (V) so as to approximately satisfy the following relationship: T=(V*8*L*C)/(V*(D&#x2212;D)).

Output voltage ripple control for a DC-DC power converter

Methods and systems for offering network-based managed security services are provided. According to one embodiment, an IP service processing switch includes multiple service blades and one or more packet-passing data rings. The service blades each have multiple processors for providing customized security services to subscribers of a service provider. Upon receipt of a packet by a service blade from the one or more packet-passing data rings, a PEID value within the packet is inspected and when the PEID value corresponds to a PEID assigned to a processor associated with the service blade, the packet is steered to a software entity of a VR on the processor that corresponds to an LQID value within the packet. And, when the PEID value does not correspond to any PEIDs assigned to processors on the service blade, the packet is passed to a next service blade on the one or more packet-passing data rings.

Packet routing system and method

A hybrid voltage rectifier enables a switch mode DC-DC power converter to safely power an external dynamic load by way of a substantially lossless conductive coupling between an output filter of the converter and the load. The rectifier is controlled so as to permit net average current through an inductor of the output filter to be approximately equal to, but not less than, zero by permitting very low loss conduction in the first quadrant and, selectively, cycle by cycle, in the third quadrant during load operation. The converter has a first switch, an output filter, a second switch, and a controller. The output filter is conductively coupled with the first switch, and has an inductor in series with the load. The controller sets state conditions of the second switch, such that the inductor operates in a continuous current mode.

Hybrid rectifier

DC-DC converters are described that employ a time-averaged modulated bypass diode to facilitate the efficient harvest of power in photovoltaic systems.

Time averaged modulated diode apparatus for photovoltaic application

A flexible, scalable hardware and software platform that allows a service provider to easily provide internet services, virtual private network services, firewall services, etc., to a plurality of customers. One aspect provides a method and system for delivering security services. This includes connecting a plurality of processors in a ring configuration within a first processing system, establishing a secure connection between the processors in the ring configuration across an internet protocol (IP) connection to a second processing system to form a tunnel, and providing both router services and host services for a customer using the plurality of processors in the ring configuration and using the second processing system, a packet routing system and method is described that includes a processor identifier in each packet to route the packets to a physical processor, and a logical queue identifier to route the packets to the destination object within that processor.

A flexible, scalable hardware and software platform that allows a service provider to easily provide internet services, virtual private network services, firewall services, etc., to a plurality of customers. One aspect provides a method and system for delivering security services. This includes connecting a plurality of processors in a ring configuration within a first processing system, establishing a secure connection between the processors in the ring configuration across an internet protocol (IP) connection to a second processing system to form a tunnel, and providing both router services and host services for a customer using the plurality of processors in the ring configuration and using the second processing system. a packet routing system and method is described that includes a processor identifier in each packet to route the packets to a physical processor, and a logical queue identifier to route the packets to the destination object within that processor.

A bus system providing increased connection flexibility and hot pluggable connections includes an open collector bus, a receiver connected to the open collector bus via a current sensor, a driver connected to the open collector bus, a peripheral card and a flexible cable operatively coupling the peripheral card, the receiver and the driver so as to provide point-to-point connection between the peripheral card and the open collector bus. The current sensor provides a control signal to the driver to increase the impedance of the driver in the event that a current is produced by the peripheral card.

Parallel telephone bus segmentation system

An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes, an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer. This assures that the read frame is always in the half of the two sample buffer not then being written to.

Integrated network switch having mixed mode switching with selectable

The present invention relates to an elastic linear buffer. The buffer is arranged in a closed loop, so that upon reaching the last address, the message is wrapped around and writing continues from the first address. Three markers are provided: a write pointer, which indicates the address of the data currently being stored; a head pointer, which indicates the last address of a previously recorded message; and a tail pointer, indicating the address of the data last read from the buffer. When the last bit of a presently received message is recorded, the head pointer is updated to indicate the address of that bit. Thereafter, a message is sent to the CPU which may commence reading of the message just received. Concurrently, a newly received message can be recorded at the addresses following the address of the head pointer up to the address of the tail pointer.

Integrated network switch with flexible serial data packet transfer

An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer. This assures that the read frame is always in the half of the two sample buffer not then being written to.

A large capacity switch architecture is disclosed, which uses a novel 'split' interface. The first part of the split interface is called a Peripheral Shelf Link Interface Unit (PSLI) and is mounted remotely from the central control. The second part is called Peripheral Interface Unit (PIU) and is mounted locally to the central control. The PSLI and the PIU are available as a copper or fiber optics dedicated unit. By selecting the appropriate matching pairs, communication can be had over a copper or fiber optics transport medium.

Integrated network switch with large capacity switch architecture using

A traditional modem includes a data access arrangement circuit located between the computer and the RJ11 connector. An alternate connection is made from this data access arrangement circuit to an input of a carbon microphone interface circuit. This carbon microphone interface circuit includes a galvanic isolation circuit and an impedance matching circuit. The input to the carbon microphone interface circuit is thus transformed to a format which is compatible with a traditional carbon microphone found in the handset of practically all telephones. Therefore, the output of the carbon microphone interface circuit can be directly connected to the handset of a telephone (or other carbon microphone audio terminal device), independent of the location or type of subscriber interface at the wall jack.

Carbon microphone interface for a modem

A method of connecting an IC card to a motherboard involves first connecting the ground busses, then the power busses and finally the general signal busses. When the power busses are connected, a low current is allowed to flow initially, then, a predetermined period of time is allowed to elapse for equalization of IC card and motherboard voltages, then a full current is allowed to flow. A method of disconnecting an IC card from a motherboard involves first disconnecting the general signal busses, then the power busses and finally the ground busses.

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Petaluma, CA, United States of America

Steven Patrick Weir