Crossbar, Inc.

Sandisk 3d LLC

Steven Patrick Maxwell

Natividad Vasquez

Mark Harold Clark

Harry Yue Gee

Yung-Tin Chen

Kun Hou

Sung Hyun Jo

Sundar Narayanan

Andrei Mihnea

Chun-Ming Wang

Michael Konevecki

Abhijit Bandyopadhyay

Chuanbin Pan

April Dawn Schricker

Steven J Radigan

Usha Raghuram

Sung-Hyun Jo

Raghuveer S Makala

Er-Xuan Ping

Christopher John Petti

Scott Brad Herner

Tanmay Kumar

Tong Zhang

Kuk-Hwan Kim

Bing K Yen

Yoichiro Tanaka

Li Xiao

Vance Dunton

Paul Wai Kie Poon

Andy Fu

Majid Milani

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Reduced diffusion in metal electrode for two-terminal memory

A method for forming a resistive switching device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring structure is formed overlying the first dielectric material. The method forms one or more first structure comprising a junction material overlying the first wiring structure. A second structure comprising a stack of material is formed overlying the first structure. The second structure includes a resistive switching material, an active conductive material overlying the resistive switching material, and a second wiring material overlying the active conductive material. The second structure is configured such that the resistive switching material is free from a coincident vertical sidewall region with the junction material.

Semiconductor device for a non-volatile (NV) resistive memory and array structure for an array of NV resistive memory

A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Recessed high voltage metal oxide semiconductor transistor for RRAM cell

Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichiometric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

Sub-oxide interface layer for two-terminal memory

A method includes patterning a layered structure comprising a monolithic stack including a bottom electrode surrounded by a dielectric material, a switching material, a barrier material, a dielectric hardmask, and a patterned photoresist formed above and adjacent to a portion of the dielectric hardmask. The patterning includes patterning the dielectric hardmask using a first etchant and employing the patterned photoresist as a mask, patterning the barrier material using a second etchant and employing a portion of the dielectric hardmask remaining after the patterning the dielectric hardmask as a mask, and patterning the switching material using ion milling or etching and employing the portion of the dielectric hardmask remaining after the patterning the barrier material as a mask.

Resistive random access memory (RRAM) cell and method for forming the RRAM cell

A memory device comprising a doped conductive polycrystalline layer having an electrically resistive portion, is described herein. By way of example, ion implantation to a subset of the conductive polycrystalline layer can degrade and modify the polycrystalline layer, forming the electrically resistive portion. The electrically resistive portion can include resistive switching properties facilitating digital information storage. Parametric control of the ion implantation can facilitate control over corresponding resistive switching properties of the resistive portion. For example, a projected range or depth of the ion implantation can be controlled, allowing for preferential placement of atoms in the resistive portion, and fine-tuning of a forming voltage of the memory device. As another example, dose and number of atoms implanted, type of atoms or ions that are implanted, the conductive polycrystalline material used, and so forth, can facilitate control over switching characteristics of the memory device.

Methods for fabricating resistive memory device switching material using ion implantation

During fabrication of a two-terminal memory device, a terminal (e.g., bottom terminal) can be formed. After formation of the terminal, a chemical mechanical planarization (CMP) process can be applied that, depending on the composition of the terminal, can cause damage that affect operating characteristics of the finished memory device or cell. In some embodiments, such damage can be removed by one or more post-CMP processes. In some embodiments, such damage can be mitigated so as to prevent the damage from occurring at all, by, e.g., forming a sacrificial layer atop the terminal prior to performing the CMP process. Thus, the sacrificial layer can operate to protect the terminal from damage resulting from the CMP process, with the remainder of the sacrificial layer being removed prior to completing the fabrication of the two-terminal memory device.

Mitigating damage from a chemical mechanical planarization process

Techniques for processing silicon germanium (SiGe) thin films to reduce surface roughness thereof are provided herein. In an aspect, a method is disclosed that includes depositing a silicon germanium (SiGe) material upon a surface of a substrate at or below about 450 degrees Celsius, the substrate having a plurality of CMOS devices therein and forming, from the deposited SiGe material, a SiGe material film, wherein the SiGe material film has a jagged surface comprising projections and indentations extended along a direction substantially perpendicular to the surface of the substrate. The method further includes performing a chemical mechanical planarization (CMP) process to the jagged surface of the SiGe material, and reducing variations between the projections and the indentions along the direction substantially perpendicular to the surface of the substrate, and transforming the jagged surface of the SiGe material into a relatively smooth surface, compared to the jagged surface.

Method for surface roughness reduction after silicon germanium thin film deposition

Scalable RRAM device architecture for a non-volatile memory device and method

A method of depositing a silver layer includes forming a plurality of openings in a dielectric layer to expose a top surface of a structure comprising a resistive memory layer on top of a p-doped silicon-containing layer on top of a conductive structure, depositing a first metal layer comprising a tungsten layer overlying the top surface of the structure, wherein a first metal material of the first metal layer contacts a resistive memory material of the resistive memory layer and exposing the first metal layer in a bath comprising a solution of silver species having an alkaline pH for a predetermined time to form a silver metal layer from the silver species from the solution overlying the resistive memory material, wherein the silver species is reduced by the first metal material, and wherein the first metal material is solubilized while forming the silver metal layer.

Method for silver deposition for a non-volatile memory device

A method of forming a resistive switching device includes forming a wiring structure over a first dielectric and substrate, forming a junction layer over the wiring structure, forming a resistive switching layer over the junction layer, forming an active metal over the resistive switching layer, forming a tungsten layer over the active metal, forming a barrier layer over the tungsten, depositing a mask over the barrier layer, etching the barrier layer to form a hard mask, etching the junction layer, the resistive switching layer, the active metal layer, and the adhesion layer using the hard mask to form a stack of material, while the adhesion layer maintains adhesion between the barrier layer and the active metal and while side walls of the stack of material have reduced contaminants and have reduced gap regions between the barrier layer and the resistive switching layer.

Electrode structure for a non-volatile memory device and method

Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication.

Low temperature deposition for silicon-based conductive film

Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO, where X can be a non-integer greater than zero and less than 2. The sub-oxide can be created in a variety of ways, including various techniques related to growing the sub-oxide, depositing the sub-oxide, or transforming an extant film into the sub-oxide.

In some embodiments, a memory cell is provided that includes a metal-insulator-metal stack and a steering element coupled to the metal-insulator-metal stack. The metal-insulator-metal stack includes a first conductive layer, a reversible resistivity switching layer above the first conductive layer, and a second conductive layer above the reversible resistivity switching layer. The first conductive layer and/or the second conductive layer includes a first semiconductor material layer. The steering element includes the first semiconductor material layer. Numerous other aspects are provided.

Growing community of inventors

Sunnyvale, CA, United States of America

Steven Patrick Maxwell