Intersil Americas Inc.

Alpha and Omega Semiconductor (cayman) Ltd.

Alpha and Omega Semiconductor International LP

Steven Patrick Laur

Rhys S A Philbrick

Nicholas Ian Archibald

M Jason Houston

Robert L Lyle, Jr

Zaki Moussaoui

Rhys Philbrick

Weihong Qiu

Ben A Dowlat

Rami Abou-Hamze

Michael Jason Houston

Thomas Andrew Jochum

Matthew Burdet Harris

Mehul Dilip Shah

Wei Dong

Zbigniew Jan Lata

Daniel Zheng

Jinyu Yang

Rhys SA Philbrick

A multi-phase current mode hysteretic modulator implements phase current balancing among the multiple power stages using slope-compensated emulated phase current signals and individual phase control signal for each phase. In some embodiments, the slope-compensated emulated phase current signals of all the phases are averaged and compared to the slope-compensated emulated phase current signal of each phase to generate a phase current balance control signal for each phase. The phase current balance control signal is combined with the voltage control loop error signal to generate a phase control signal for each phase where the phase control signals are generated for the multiple phases to control the phase current delivered by each power stage.

Multi-phase switching regulator incorporating phase current balance circuit

A controller for a switching regulator receiving an input voltage and generating a regulated output voltage includes a buck control circuit and a boost control circuit. The controller activates the buck control circuit to generate the regulated output voltage having a first voltage value less than the input voltage. The controller activates the boost control circuit to return charges stored on the output capacitor at the output node to the input node, thereby driving the regulated output voltage to a second voltage value lower than the first voltage value. In some embodiments, in response to a command instructing the controller to allow the output voltage to decay, the controller operates in the boost mode using the boost control circuit to recycle the stored charge at the output node while ramping down the output voltage.

Switching regulator implementing power recycling

A current mode control modulation includes a ramp signal generator generating a slope compensated ramp signal with slope compensation. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator includes a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit to generate the ramp signal with slope compensation.

Current mode control modulator including ramp signal generator providing slope compensation

Multi-phase switching regulator with variable gain phase current balancing using slope-compensated emulated phase current signals

An apparatus, comprising, a MOSFET, a controller coupled to the MOSFET, an inductor conductively coupled to the MOSFET. A reported current output of the controller is adjusted based on a predetermined excursion of an attribute of the inductor from a fixed attribute value.

Inductor binning enhanced current sense

An error amplifier circuit receives first and second input signals and provides an error amplifier output signal indicative of the difference between the first and second input signals. The error amplifier circuit implements a proportional-integrator-differentiator (PID) circuit having a differential input signal path and including a proportional amplifier circuit, an integrator amplifier circuit, and a differentiator amplifier circuit. The differentiator amplifier circuit receives an AC coupled input signal. The error amplifier circuit sums the output from the proportional amplifier circuit, the integrator amplifier circuit and the differentiator amplifier circuit to provide the error amplifier output signal where the error amplifier output signal is referenced to a first bias voltage.

Digitally programmable, fully differential error amplifier

A ramp signal generator generates a slope compensated ramp signal with optimal slope compensation for a current mode control modulator. In some embodiments, the ramp signal generator generates a ramp signal for the current control loop having a first ramp portion with slope compensation and a second ramp portion that matches the expected current mode signal. In some embodiments, the ramp signal generator is implemented using a switched capacitor circuit with charge scaling to generate the ramp signal with optimal slope compensation built into the ramp signal.

Slope compensation for current mode control modulator

A voltage-controlled oscillator (VCO) generates a clock signal in response to an input feedback signal by applying tuning to a control loop error signal related to the input feedback signal and generating the clock signal using a voltage ramp signal that is ground referenced. The VCO includes an input tuning circuit applying tuning to a difference signal to generate a tuned voltage signal, a comparator to compare the tuned voltage signal to the ground-based ramp signal, an one-shot circuit to generate an one-shot signal pulse in response to the ramp signal increasing to the tuned voltage signal. The one-shot signal pulse is the clock signal and is also used to reset the ramp signal. In some embodiments, the voltage-controlled oscillator of the present disclosure is incorporated in a current mode hysteretic modulator.

Voltage-controlled oscillator for current mode hysteretic modulator

Slope compensation for peak current mode control modulator

A circuit for providing temperature compensation to a sense signal having a first temperature coefficient includes a temperature compensation circuit receiving a temperature sense signal indicative of a temperature associated with the sense signal where the temperature compensation circuit is digitally configurable by at least one digital signal to generate a compensating impedance signal having a second temperature coefficient. The compensating impedance signal provides an impedance value in response to the temperature sense signal. The compensating impedance signal is applied to modify the sense signal to provide a modified sense signal having substantially zero temperature coefficient over a first frequency range. The circuit further includes an amplifier circuit receiving the modified sense signal and generating an output signal indicative of the sense signal where the output signal has substantially zero temperature coefficient over the first frequency range.

DC resistance sense temperature compensation

One embodiment pertains to a method including determining the duty cycle of a PWM signal, operating in valley current control mode when the duty cycle is greater than fifty percent, operating in peak current control mode when the duty cycle is less than fifty percent, and including, commencing a PWM pulse upon the occurrence of a pulse of a first clock signal pulse, and terminating the PWM pulse upon a level of a signal exceeding a positive window threshold.

Method and system for reducing transients in DC-DC converters

The system and method creates a substantially constant output voltage ripple in a buck converter in discontinuous conduction mode by varying the on-time of a pulse width modulator (PWM) signal driving the buck converter when the buck converter is operating in discontinuous conduction mode. A first signal is generated that is a function of the switching frequency of the buck converter. This signal is low-pass filtered and compared with a second signal that is a function of the switching frequency of the buck converter when operating in continuous conduction mode and with constant PWM on-time. The output signal generated by the comparator is a signal that is equal to the ratio of the first signal and the second signal. The on-time of a voltage controlled oscillator is controlled by the output signal, the oscillator signal causing the on-time of the PWM signal to vary in a controlled fashion.

System and method for maintaining a constant output voltage ripple in a buck converter in discontinuous conduction mode

A controller for controlling operation of a switching regulator including a modulator, a discontinuous conduction mode (DCM) controller, an audible DCM (ADCM) controller, and a sub-sonic discontinuous conduction mode (SBDCM) controller. The modulator generally operates in a continuous conduction mode. The DCM controller modifies operation to DCM during low loads. The ADCM controller detects when the switching frequency is less than a super-sonic frequency threshold and modifies operation to maintain the switching frequency at a super-sonic frequency level. The SBDCM controller detects a sub-sonic operating condition during ADCM operation and responsively inhibits operation of the ADCM mode controller to allow a SBDCM mode within a sub-sonic switching frequency range. The SBDCM operating mode allows for efficient connected standby operation. The SBDCM controller allows operation to return to other modes when the switching frequency increases above the subsonic level.

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Raleigh, NC, United States of America

Steven Patrick Laur