Fairchild Semiconductor Corporation

Steven Park

Jun Cai

Alvin Sugerman

A process for forming a vertical DMOS device with an ESD protection transistor that is configured for carrying a breakdown current includes the steps of masking a substrate of a first polarity type and forming spaced apart surface isolation regions. An insulated gate is formed between the spaced apart surface isolation regions. Selected portions of the surface regions between the gate and the surface isolation regions are heterodoped to form p-n junctions having retrograde doping profiles beneath the substrate surface thereby lowering the breakdown voltage beneath the heterodoped portions in order to direct a substantial portion of the breakdown current below the surface of the substrate and into the body of the substrate between the heterodoped regions. Source and drain regions are formed in the substrate surface on opposite sides of the gate.

ESD protection for semiconductor products

Devicein FIG.has junctionseach with a lateral portionand a second portionextending upward toward the surfacefrom the lateral portion. The lateral portions, as illustrated in FIG., are more or less formed along a plane parallel with the surface. The upwardly extending portionsinclude characteristic curved edges of the diffusion fronts which are associated with the planar process. With the regionsandeach having relatively high net dopant concentrations of different conductivity types, each lateral junction portionincludes a relatively large sub regionwhich extends more deeply into the layer. When compared to other portions of the junctions, the subregionsare characterized by a relatively low breakdown voltage so that ESD current is initially directed vertically rather than laterally.

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Falmouth, ME, United States of America

Steven Park