Xilinx, Inc.

Other

Steven P Young

Trevor J Bauer

Brian C Gaide

Bernard J New

Venu M Kondapalli

Kamal Chaudhary

F Erich Goetting

David P Schultz

Michael J Hart

Martin L Voogel

Jennifer Wong

Vasisht Mantra Vadi

Suresh M Menon

Roman Iwanczuk

Alvin Y Ching

Ramakrishna K Tanikella

Atul V Ghia

Raymond C Pang

Shekhar Bapat

Richard A Carberry

James M Simkins

Adebabay M Bekele

Scott O Frake

Bruce E Talley

Manoj Chirania

Philip D Costello

Stephen M Trimberger

Peter H Alfke

Sridhar Krishnamurthy

Warren E Cory

Jason R Bergendahl

Austin H Lesea

James Karp

Patrick J Crotty

Joseph H Hassoun

Paul Ying-Fung Wu

Zicheng Gary Ling

Stephen M Douglass

Mehul R Vashi

Jeffrey V Lindholm

Jane W Sowards

Ketan Sodha

Xiao-Jie Yuan

Robert O Conn

Jan Lodewijk De Jong

Alireza S Kaviani

David Erich Tetzlaff

Shahin Toutounchi

Kevin T Look

Thanh Ngoc Pham

Ping-Chen Liu

Weiguang Lu

Paul T Sasaki

Eric F Dellinger

Eric E Edwards

Christopher D Ebeling

Carl H Carmichael

Tien Duc Pham

Nigel G Herron

Nicolas J Camilleri

William Edward Allaire

Kwansuhk Oh

Arthur Behiel

Andrew K Percey

Scott S Nance

Ramakrishna Kishore Tanikella

Kenneth D Chapman

Paul-Hugo Lamarche

Arifur Rahman

Ahmad R Ansari

Ralph D Wittig

Sundararajarao Mohan

Marwan M Hassoun

Matthew H Klein

Santosh Yachareni

Christopher H Kingsley

Moises Emanuel Robinson

Robert W Wells

Nui Chong

Dinesh D Gaitonde

Robert Yin

John D Logue

Jay T Young

Daniel Gitlin

Robert D Patrie

Hua Shen

Shidong Zhou

Richard William Swanson

Praful Jain

Daniel Y Chung

Wilson Kaming Yee

Santosh Kumar Sood

Lawrence C Hung

Anil Kumar Kandala

Tao Pi

Robert M Ondris

Robert I Fu

Sanjiv Stokes

Chirag Ravishankar

Daniel J Ferris, Iii

An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.

Compute dataflow architecture

An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

Power delivery network for active-on-active stacked integrated circuits

Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.

Multi-chip stacked devices

Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

Redundancy scheme for multi-chip stacked devices

A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements

In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

Distributed multi-die routing in a multi-chip module

In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

Lut cascading circuit

A method for caring for a lawn and an apparatus for providing lawn care are provided. The method includes steps of powering an electrically powered lawn care device by a electric power source, wherein the electric power source is provided as part of an electrically powered transportation vehicle, and treating the lawn by using the electrically powered lawn care device. The apparatus includes: (a) a hybrid vehicle having an electric motor for driving the hybrid vehicle, and an electric power source for powering the electric motor; (b) a trailer constructed to attach to the hybrid vehicle so that the trailer can be pulled by the hybrid vehicle; and (c) electrically powered lawn care equipment constructed to fit within the trailer, and wherein the electric power source is constructed to power the electrically powered lawn care equipment.

Method and apparatus for lawn care

An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer

A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Circuits for and methods of controlling power within an integrated circuit

A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.

Signed multiplier circuit utilizing a uniform array of logic blocks

A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.

Two gate pitch FPGA memory cell

A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.

Method and apparatus to reduce power segmentation overhead within an integrated circuit

A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.

Circuits for shifting bussed data

Growing community of inventors

Boulder, CO, United States of America

Steven P Young