Sun Microsystems, Inc.

Encore Computer U.s., Inc.

Steven P Kent

John D Acton

Jack M Hardy, Jr

Steven E Schelong

Gavin G Gibson

Michael D Derbish

Hugh M Humphreys

William B DeRolf

Ricardo Yong

Lawrence C Grant

A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

Data processing system including a shared memory resource circuit

A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.

Computing system having multiple nodes coupled in series in a closed loop

Multiprocessor distributed memory system and board and methods therefor

A system for coupling sets of plurality of nodes that are memory coupled to pass write only data memory to memory via a data link that further includes an optical fiber controller coupled to each data link. Each controller is interconnected through fiber for high speed data transfers from one set of nodes to another. The controller is capable of connection implementing three and four cable interfaces. The data is transmitted through the fiber serially but the controller is adapted to receive parallel data and convert to serial form and vice versa.

Fiber optic memory coupling system with converter transmitting and

Growing community of inventors

Sunrise, FL, United States of America

Steven P Kent