Ati International Srl

Ati Technologies Inc.

Advanced Micro Devices Corporation

Ati Technologies Ulc

Steven Morein

Michael T Wright

Lin Chen

Ming-Ju Edward Lee

Joseph D Macri

Claude R Gauthier

Laurent Lefebvre

Andi Skende

Andy Gruber

Kin M Yee

John Edward DeRoo

Brian Favela

Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.

Low power mode unipolar current/voltage mode interface

Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

Fast transition from low-speed mode to high-speed mode in high-speed interfaces

A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.

Method and system for communicated client phase information during an idle period of a data bus

A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

Graphics processing architecture employing a unified shader

A method and apparatus for managing compressed Z information in a video graphics system is described. Pixels in a display frame are grouped into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. When possible, the Z information corresponding to the plurality of pixels in a pixel block is compressed and stored in a Z buffer in a compressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates a level of compression of the Z information for each of the pixel blocks. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block. Based on the indication provided by the Z mask memory as to the level of compression, a predetermined amount of data is retrieved from the Z buffer, and when the Z information is in compressed format, it is decompressed. The fetched Z information is then stored in the cache for use in video graphics processing.

Method and apparatus for controlling compressed Z information in a video graphics system

A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials. An output format representation of the planar differential slope representation is then generated, where encoding of the slope differentials allows the parameter values for the pixel block to be compressed. This compressed format representation of the parameter values can then be stored in and retrieved from memory.

Method and apparatus for compressing parameter values for pixels in a display frame

A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame. The render backend block combines fragments received from the first and second caches with portions of the current pixel information in the frame buffer to produce revised pixel information that is stored back in the frame buffer. The combination operations performed by the render backend block utilize the state information stored in one of the first and second sets of state registers based on from which fragment cache the fragment being combined originated. A control block that is operably coupled to the first and second fragment caches and the first and second sets of state registers initially routes received fragments to the first fragment cache. When a state change occurs, the control block alters the flow of fragments such that subsequent fragments are routed to the second fragment cache while the first fragment cache is flushed. Flushing the first fragment cache includes providing all of the pixel fragments included in the first fragment cache to the render backend block along with the old state variables that are stored in the first set of state registers.

Dual fragment-cache pixel processing circuit and method therefore

A method and apparatus for managing compressed Z information in a video graphics system that supports anti-aliasing is described. Each pixel in the display frame is represented with a primary Z value, a secondary Z value, a first and second color, and a pixel mask that indicates how the Z values and colors apply to the samples of the pixel. The primary Z values for the pixels in a pixel block are then compressed using a compression algorithm and stored in a Z buffer in a compressed format. A secondary mask that indicates which pixels in the pixel block have valid secondary Z values is also stored in the Z buffer, along with the secondary Z values and the pixel masks in an uncompressed format. A Z mask value for each pixel block in the frame is stored in a Z mask memory, where the Z mask for each pixel block indicates the level of compression of the Z information the corresponding pixel block. When Z information for a pixel block is required for processing operations, a cache is first examined to determine if the Z information for the pixel block is included in the cache. If the Z information is not included in the cache, the Z mask memory is consulted to determine the level of compression of the Z information for the particular pixel block. Based on the indication provided by the Z mask memory as to the level of compression, a predetermined amount of buffered Z information is retrieved from the Z buffer, and when the Z information is in compressed format, it is decompressed. The fetched Z information is then stored in the cache for use in video graphics processing.

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Cambridge, MA, United States of America

Steven Morein