Micron Technology Incorporated

Oracle America, Inc.

Storage Technology Corporation

Sun Microsystems, Inc.

Steven Michael Kientz

Michael Sheperek

Bruce A Liikanen

Vamsi Pavan Rayaprolu

Larry Joseph Koudele

Shane G Nowell

Mustafa Nazmi Kaynak

Kishore Kumar Muchherla

Peter Sean Feeley

Patrick Robert Khayat

Sivagnanam Parthasarathy

Chia-Yu Kuo

Ugo Russo

Pitamber Shukla

Matthew P Wojciechowski

Robert W Mason

Renato C Padilla

Gary F Besinga

Steven Gregory Trabert

Mark Lee Watson

Christopher M Smitchger

David Lyle Peterson

Michael S Wagner

Hyung Seok Kim

Kevin D Mckinstry

One or more trim values associated with a set of blocks of a memory device are set according to a representative number of program erase cycles (PECs) for the set of blocks. Each block in the set of blocks was programmed within at least one of a specified time window or a specified temperature range. Responsive to executing a program operation on a block of the set of blocks according to the one or more trim values, an indicator is set to reflect the one or more trim values used during the execution of the program operation. Responsive to receiving a request to perform a read operation directed to the block of the set of blocks, a read offset value corresponding to the indicator is determined. The read operation is performed using the read offset value.

Charge loss mitigation throughout memory device lifecycle by proactive window shift

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including initializing the memory device; selecting at least one sample management unit on the memory device; performing a calibration operation on the sample management unit to determine a duration value reflecting a duration during which the memory device was powered down; adjusting an accumulator value based on the duration value; determining a read voltage value based on the accumulator value; and performing a read operation using the read voltage value.

Determining read voltage offset in memory devices

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Block family-based error avoidance for memory devices

A system includes a memory device and a processing device to initialize a block family associated with the memory device and a timer at initialization of the block family. The processing device further stores, in non-volatile memory of the memory device, a value of the timer before powering down the system while the block family is still open. The processing device further detects a power on of the system and measures a data state metric associated with one or more memory cell of a page of the memory device that is associated with the block family. The processing device further compares a level of the data state metric to a temporal voltage shift function to estimate a time after program value of the page and increments the value of the timer, restored from the non-volatile memory, based on the time after program value.

Open block family duration limited by time and temperature

A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Temperature-compensated time estimate for a block to reach a uniform charge loss state

A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Measurement of representative charge loss in a block to determine charge loss state

An example method of threshold voltage offset calibration at memory device power up comprises: identifying a set of memory pages that have been programmed within a time window; determining, for each voltage offset bin of a plurality of voltage offset bins, a corresponding value of a data state metric produced by a memory access operation with respect to a memory page of the set of memory pages, wherein the memory access operation utilizes a voltage offset associated with the voltage offset bin; identifying a subset of the plurality of voltage offset bins, such that memory access operations performed using the corresponding voltage offsets produced respective values of the data state metric that satisfy a predefined quality criterion; selecting, among the subset of the plurality of voltage offset bins, a voltage offset bin that is associated with the lowest voltage offset; and associating the set of memory pages with the selected voltage offset bin.

Threshold voltage bin calibration at memory device power up

A first analysis of each respective die of a multi-die memory device is performed. An equation to determine a respective temperature compensation (tempco) value for each respective die based on a number of program erase cycles (PECs) of the respective die based on the first analysis s determined. The equation for use in processing memory access requests directed to the respective die is stored. Whether to update the equation directed to the respective die based on a second analysis of the respective die is determined.

Adaptive temperature compensation for a memory device

A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including detecting a power up event of the memory device, responsive to detecting the power up event, selecting an open block of the memory device, wherein the open block comprises a set of pages, determining, based at least in part on an analysis of the set of pages, whether the open block is valid for programming, and responsive to determining that the open block is valid for programming, keeping the open block open for programming.

Program continuation strategies after memory device power loss

An example method of two-stage voltage calibration upon power-up of a memory device comprises: identifying a set of memory pages that have been programmed within a time window; responsive to detecting a power up event, performing a first calibration operation with respect to the set of memory pages to determine a first value of a data state metric; identifying, among a plurality of voltage offset bins, a first voltage offset bin corresponding to the first value of the data state metric; storing, in a temporary metadata table, a first record associating the set of memory pages with the first voltage offset bin; performing a second calibration operation with respect to the set of memory pages to determine a second value of the data state metric, wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation; identifying, among a plurality of voltage offset bins, a second voltage offset bin corresponding to the second value of the data state metric; and storing, in a permanent metadata table, a record associating the set of memory pages with the second voltage offset bin.

Two-stage voltage calibration upon power-up of memory device

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including periodically, at a predefined frequency, incrementing a value stored in an accumulator by a composite parameter value; responsive to receiving a program request specifying a data item to be programmed to a management unit of the memory device, obtaining a first value from the accumulator; storing the first value to a program reference table; programming the data item to the management unit; responsive to receiving a read request specifying the management unit, obtaining a second value from the accumulator; determining a read voltage value based on a difference of the first value and the second value; and performing a read operation, using the read voltage value, on the management unit.

A system includes a memory device including an block and a processing device, operatively coupled with the memory device, to perform operations including initiating a page scan with respect to a page of the block, determining whether to perform an erased page check, and in response to determining that the erased page check is not to be performed, performing a two-sided page scan with calibration feedback.

Two-sided page scans with calibration feedback

An average number of program erase cycles (PECs) for a memory device is identified. A set of trims associated with the average number of PECs is identified. One or more write trims associated with the memory device are set according to the set of trims. A write command directed to the memory device is received. The write command is executed according to the one or more write trims.

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to detecting a triggering event, selecting a family of memory blocks of the memory device, the selected family being associated with a set of bins, each bin associated with a plurality of read voltage offsets to be applied to base read voltages during read operations. The operations performed by the processing device further include calibration operations to determine data state metric values characterizing application of read voltage offsets of various bins. The operations performed by the processing device further include identifying, based on the determined data state metrics, a target bin and associating the selected family with the target bin.

Growing community of inventors

Westminster, CO, United States of America

Steven Michael Kientz